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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
277 lines
6.6 KiB
C
277 lines
6.6 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/io/io_block.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include "uniphier.h"
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#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READSTART 0x30
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#define DENALI_ECC_ENABLE 0x0e0
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#define DENALI_PAGES_PER_BLOCK 0x150
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#define DENALI_DEVICE_MAIN_AREA_SIZE 0x170
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#define DENALI_DEVICE_SPARE_AREA_SIZE 0x180
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#define DENALI_TWO_ROW_ADDR_CYCLES 0x190
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#define DENALI_INTR_STATUS0 0x410
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#define DENALI_INTR_ECC_UNCOR_ERR BIT(1)
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#define DENALI_INTR_DMA_CMD_COMP BIT(2)
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#define DENALI_INTR_INT_ACT BIT(12)
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#define DENALI_DMA_ENABLE 0x700
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#define DENALI_HOST_ADDR 0x00
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#define DENALI_HOST_DATA 0x10
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#define DENALI_MAP01 (1 << 26)
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#define DENALI_MAP10 (2 << 26)
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#define DENALI_MAP11 (3 << 26)
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#define DENALI_MAP11_CMD ((DENALI_MAP11) | 0)
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#define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1)
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#define DENALI_MAP11_DATA ((DENALI_MAP11) | 2)
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#define DENALI_ACCESS_DEFAULT_AREA 0x42
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#define UNIPHIER_NAND_BBT_UNKNOWN 0xff
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struct uniphier_nand {
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uintptr_t host_base;
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uintptr_t reg_base;
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int pages_per_block;
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int page_size;
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int two_row_addr_cycles;
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uint8_t bbt[16];
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};
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struct uniphier_nand uniphier_nand;
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static void uniphier_nand_host_write(struct uniphier_nand *nand,
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uint32_t addr, uint32_t data)
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{
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mmio_write_32(nand->host_base + DENALI_HOST_ADDR, addr);
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mmio_write_32(nand->host_base + DENALI_HOST_DATA, data);
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}
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static uint32_t uniphier_nand_host_read(struct uniphier_nand *nand,
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uint32_t addr)
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{
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mmio_write_32(nand->host_base + DENALI_HOST_ADDR, addr);
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return mmio_read_32(nand->host_base + DENALI_HOST_DATA);
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}
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static int uniphier_nand_block_isbad(struct uniphier_nand *nand, int block)
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{
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int page = nand->pages_per_block * block;
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int column = nand->page_size;
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uint8_t bbm;
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uint32_t status;
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int is_bad;
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/* use cache if available */
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if (block < ARRAY_SIZE(nand->bbt) &&
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nand->bbt[block] != UNIPHIER_NAND_BBT_UNKNOWN)
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return nand->bbt[block];
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mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 0);
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mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1);
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uniphier_nand_host_write(nand, DENALI_MAP11_CMD, NAND_CMD_READ0);
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uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, column & 0xff);
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uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, (column >> 8) & 0xff);
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uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, page & 0xff);
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uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, (page >> 8) & 0xff);
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if (!nand->two_row_addr_cycles)
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uniphier_nand_host_write(nand, DENALI_MAP11_ADDR,
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(page >> 16) & 0xff);
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uniphier_nand_host_write(nand, DENALI_MAP11_CMD, NAND_CMD_READSTART);
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do {
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status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0);
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} while (!(status & DENALI_INTR_INT_ACT));
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bbm = uniphier_nand_host_read(nand, DENALI_MAP11_DATA);
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is_bad = bbm != 0xff;
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/* if possible, save the result for future re-use */
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if (block < ARRAY_SIZE(nand->bbt))
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nand->bbt[block] = is_bad;
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if (is_bad)
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WARN("found bad block at %d. skip.\n", block);
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return is_bad;
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}
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static int uniphier_nand_read_pages(struct uniphier_nand *nand, uintptr_t buf,
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int page_start, int page_count)
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{
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uint32_t status;
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mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 1);
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mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 1);
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mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1);
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/* use Data DMA (64bit) */
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mmio_write_32(nand->host_base + DENALI_HOST_ADDR,
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DENALI_MAP10 | page_start);
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/*
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* 1. setup transfer type, interrupt when complete,
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* burst len = 64 bytes, the number of pages
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*/
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mmio_write_32(nand->host_base + DENALI_HOST_DATA,
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0x01002000 | (64 << 16) | page_count);
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/* 2. set memory low address */
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mmio_write_32(nand->host_base + DENALI_HOST_DATA, buf);
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/* 3. set memory high address */
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mmio_write_32(nand->host_base + DENALI_HOST_DATA, buf >> 32);
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do {
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status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0);
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} while (!(status & DENALI_INTR_DMA_CMD_COMP));
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mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 0);
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if (status & DENALI_INTR_ECC_UNCOR_ERR) {
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ERROR("uncorrectable error in page range %d-%d",
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page_start, page_start + page_count - 1);
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return -EBADMSG;
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}
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return 0;
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}
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static size_t __uniphier_nand_read(struct uniphier_nand *nand, int lba,
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uintptr_t buf, size_t size)
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{
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int pages_per_block = nand->pages_per_block;
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int page_size = nand->page_size;
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int blocks_to_skip = lba / pages_per_block;
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int pages_to_read = DIV_ROUND_UP(size, page_size);
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int page = lba % pages_per_block;
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int block = 0;
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uintptr_t p = buf;
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int page_count, ret;
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while (blocks_to_skip) {
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ret = uniphier_nand_block_isbad(nand, block);
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if (ret < 0)
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goto out;
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if (!ret)
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blocks_to_skip--;
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block++;
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}
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while (pages_to_read) {
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ret = uniphier_nand_block_isbad(nand, block);
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if (ret < 0)
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goto out;
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if (ret) {
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block++;
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continue;
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}
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page_count = MIN(pages_per_block - page, pages_to_read);
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ret = uniphier_nand_read_pages(nand, p,
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block * pages_per_block + page,
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page_count);
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if (ret)
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goto out;
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block++;
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page = 0;
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p += page_size * page_count;
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pages_to_read -= page_count;
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}
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out:
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/* number of read bytes */
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return MIN(size, p - buf);
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}
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static size_t uniphier_nand_read(int lba, uintptr_t buf, size_t size)
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{
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size_t count;
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inv_dcache_range(buf, size);
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count = __uniphier_nand_read(&uniphier_nand, lba, buf, size);
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inv_dcache_range(buf, size);
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return count;
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}
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static struct io_block_dev_spec uniphier_nand_dev_spec = {
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.buffer = {
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.offset = UNIPHIER_BLOCK_BUF_BASE,
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.length = UNIPHIER_BLOCK_BUF_SIZE,
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},
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.ops = {
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.read = uniphier_nand_read,
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},
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/* fill .block_size at run-time */
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};
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static int uniphier_nand_hw_init(struct uniphier_nand *nand)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(nand->bbt); i++)
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nand->bbt[i] = UNIPHIER_NAND_BBT_UNKNOWN;
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nand->host_base = 0x68000000;
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nand->reg_base = 0x68100000;
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nand->pages_per_block =
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mmio_read_32(nand->reg_base + DENALI_PAGES_PER_BLOCK);
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nand->page_size =
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mmio_read_32(nand->reg_base + DENALI_DEVICE_MAIN_AREA_SIZE);
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if (mmio_read_32(nand->reg_base + DENALI_TWO_ROW_ADDR_CYCLES) & BIT(0))
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nand->two_row_addr_cycles = 1;
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uniphier_nand_host_write(nand, DENALI_MAP10,
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DENALI_ACCESS_DEFAULT_AREA);
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return 0;
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}
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int uniphier_nand_init(uintptr_t *block_dev_spec)
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{
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int ret;
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ret = uniphier_nand_hw_init(&uniphier_nand);
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if (ret)
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return ret;
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uniphier_nand_dev_spec.block_size = uniphier_nand.page_size;
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*block_dev_spec = (uintptr_t)&uniphier_nand_dev_spec;
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return 0;
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}
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