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18af644279
DDR4 Chip is EOL during redesign of ls1043ardb pd version. The replacement from MT is MT40A1G8SA-062E:R. New ddr configure is compatible with both pd and old version of ls1043ardb. Signed-off-by: Chunlei Xu <chunlei.xu@nxp.com> Change-Id: I714c091a2cf15046438d0723fb55a4410c386ef4
163 lines
3.5 KiB
C
163 lines
3.5 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <common/debug.h>
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#include <ddr.h>
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#include <lib/utils.h>
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#include <errata.h>
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#include <platform_def.h>
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#ifdef CONFIG_STATIC_DDR
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const struct ddr_cfg_regs static_1600 = {
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.cs[0].config = U(0x80040322),
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.cs[0].bnds = U(0x7F),
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.sdram_cfg[0] = U(0xC50C0000),
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.sdram_cfg[1] = U(0x401100),
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.timing_cfg[0] = U(0x91550018),
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.timing_cfg[1] = U(0xBBB48C42),
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.timing_cfg[2] = U(0x48C111),
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.timing_cfg[3] = U(0x10C1000),
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.timing_cfg[4] = U(0x2),
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.timing_cfg[5] = U(0x3401400),
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.timing_cfg[7] = U(0x13300000),
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.timing_cfg[8] = U(0x2115600),
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.sdram_mode[0] = U(0x3010210),
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.sdram_mode[9] = U(0x4000000),
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.sdram_mode[8] = U(0x500),
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.sdram_mode[2] = U(0x10210),
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.sdram_mode[10] = U(0x400),
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.sdram_mode[11] = U(0x4000000),
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.sdram_mode[4] = U(0x10210),
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.sdram_mode[12] = U(0x400),
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.sdram_mode[13] = U(0x4000000),
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.sdram_mode[6] = U(0x10210),
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.sdram_mode[14] = U(0x400),
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.sdram_mode[15] = U(0x4000000),
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.interval = U(0x18600618),
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.zq_cntl = U(0x8A090705),
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.clk_cntl = U(0x3000000),
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.cdr[0] = U(0x80040000),
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.cdr[1] = U(0xA181),
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.wrlvl_cntl[0] = U(0x8675F607),
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.wrlvl_cntl[1] = U(0x7090807,
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.wrlvl_cntl[2] = U(0x7070707),
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.debug[28] = U(0x00700046),
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};
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uint64_t board_static_ddr(struct ddr_info *priv)
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{
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memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
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return ULL(0x80000000);
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}
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#else
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static const struct rc_timing rcz[] = {
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{1600, 12, 7},
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{}
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};
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static const struct board_timing ram[] = {
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{0x1f, rcz, 0x00020100, 0},
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};
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int ddr_board_options(struct ddr_info *priv)
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{
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int ret;
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struct memctl_opt *popts = &priv->opt;
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ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
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if (ret)
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return ret;
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popts->cpo_sample = U(0x46);
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
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DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
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return 0;
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}
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/* DDR model number: MT40A1G8SA-062E:R */
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struct dimm_params ddr_raw_timing = {
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.n_ranks = U(1),
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.rank_density = ULL(2147483648),
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.capacity = ULL(2147483648),
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.primary_sdram_width = U(32),
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.ec_sdram_width = U(4),
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.rdimm = U(0),
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.mirrored_dimm = U(0),
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.n_row_addr = U(16),
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.n_col_addr = U(10),
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.bank_group_bits = U(2),
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.edc_config = U(2),
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.burst_lengths_bitmask = U(0x0c),
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.tckmin_x_ps = 625,
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.tckmax_ps = 2200,
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.caslat_x = U(0x0001FFE00),
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.taa_ps = 13500,
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.trcd_ps = 13500,
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.trp_ps = 13500,
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.tras_ps = 32000,
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.trc_ps = 45500,
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.twr_ps = 15000,
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.trfc1_ps = 350000,
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.trfc2_ps = 260000,
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.trfc4_ps = 160000,
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.tfaw_ps = 21000,
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.trrds_ps = 3000,
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.trrdl_ps = 4900,
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.tccdl_ps = 5000,
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.refresh_rate_ps = U(7800000),
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.rc = U(0x1f),
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};
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int ddr_get_ddr_params(struct dimm_params *pdimm,
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struct ddr_conf *conf)
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{
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static const char dimm_model[] = "Fixed DDR on board";
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conf->dimm_in_use[0] = 1;
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memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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return 1;
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}
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#endif
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int64_t init_ddr(void)
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{
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struct ddr_info info;
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struct sysinfo sys;
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int64_t dram_size;
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zeromem(&sys, sizeof(sys));
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get_clocks(&sys);
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debug("platform clock %lu\n", sys.freq_platform);
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debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
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debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
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zeromem(&info, sizeof(struct ddr_info));
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info.num_ctlrs = 1;
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info.dimm_on_ctlr = 1;
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info.clk = get_ddr_freq(&sys, 0);
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info.ddr[0] = (void *)NXP_DDR_ADDR;
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dram_size = dram_init(&info);
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if (dram_size < 0) {
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ERROR("DDR init failed\n");
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}
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#ifdef ERRATA_SOC_A008850
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erratum_a008850_post();
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#endif
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return dram_size;
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}
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