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79626f460f
This patch is used to implement 1. Cold/Warm reset and SMP support for Agilex5 SoC FPGA 2. Updated product name -> Agilex5 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d
51 lines
1.6 KiB
C
51 lines
1.6 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <platform_def.h>
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#include <lib/psci/psci.h>
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static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
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/*******************************************************************************
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* This function returns the default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return plat_power_domain_tree_desc;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id;
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mpidr &= MPIDR_AFFINITY_MASK;
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
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return -1;
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cluster_id = (mpidr >> PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> PLAT_CPU_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK;
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if (cluster_id >= PLATFORM_CLUSTER_COUNT)
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return -1;
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/*
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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*/
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
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return -1;
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return (cpu_id + (cluster_id * 4));
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}
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