2 commits

Author	SHA1	Message	Date
Jit Loon Lim	79626f460f	feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA ... This patch is used to implement 1. Cold/Warm reset and SMP support for Agilex5 SoC FPGA 2. Updated product name -> Agilex5 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d	2023-07-05 09:08:34 +08:00
Hadi Asyrafi	d8820789ca	intel: Platform common code refactor ... Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc	2019-08-01 16:39:27 +08:00

Renamed from plat/intel/soc/agilex/socfpga_topology.c (Browse further)