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https://github.com/ARM-software/arm-trusted-firmware.git
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68bb3e836e
After a calibration we cannot trust the DDR content. Let's explicitly clear the DDR content using the built-in scrubber in this case. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I6f429623f76a21f61f85efbb660cf65d99c04f56
168 lines
4.9 KiB
C
168 lines
4.9 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DDR_H
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#define DDR_H
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#include <lib/mmio.h>
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#include "socfpga_handoff.h"
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enum ddr_type {
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DDR_TYPE_LPDDR4_0,
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DDR_TYPE_LPDDR4_1,
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DDR_TYPE_DDR4,
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DDR_TYPE_LPDDR5_0,
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DDR_TYPE_LPDDR5_1,
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DDR_TYPE_DDR5,
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DDR_TYPE_UNKNOWN
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};
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/* Region size for ECCCFG0.ecc_region_map */
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enum region_size {
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ONE_EIGHT,
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ONE_SIXTEENTH,
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ONE_THIRTY_SECOND,
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ONE_SIXTY_FOURTH
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};
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/* DATATYPE DEFINATION */
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typedef unsigned long long phys_addr_t;
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typedef unsigned long long phys_size_t;
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/* MACRO DEFINATION */
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#define IO96B_0_REG_BASE 0x18400000
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#define IO96B_1_REG_BASE 0x18800000
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#define IO96B_CSR_BASE 0x05000000
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#define IO96B_CSR_REG(reg) (IO96B_CSR_BASE + reg)
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#define IOSSM_CMD_MAX_WORD_SIZE 7U
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#define IOSSM_RESP_MAX_WORD_SIZE 4U
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#define CCU_REG_BASE 0x1C000000
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#define DMI0_DMIUSMCTCR 0x7300
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#define DMI1_DMIUSMCTCR 0x8300
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#define CCU_DMI_ALLOCEN BIT(1)
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#define CCU_DMI_LOOKUPEN BIT(2)
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#define CCU_REG(reg) (CCU_REG_BASE + reg)
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// CMD_RESPONSE_STATUS Register
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#define CMD_RESPONSE_STATUS 0x45C
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#define CMD_RESPONSE_OFFSET 0x4
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#define CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16)
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#define CMD_RESPONSE_DATA_SHORT_OFFSET 16
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#define STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5)
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#define STATUS_CMD_RESPONSE_ERROR_OFFSET 5
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#define STATUS_GENERAL_ERROR_MASK GENMASK(4, 1)
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#define STATUS_GENERAL_ERROR_OFFSET 1
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#define STATUS_COMMAND_RESPONSE_READY 0x1
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#define STATUS_COMMAND_RESPONSE_READY_CLEAR 0x0
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#define STATUS_COMMAND_RESPONSE_READY_MASK 0x1
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#define STATUS_COMMAND_RESPONSE_READY_OFFSET 0
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#define STATUS_COMMAND_RESPONSE(x) (((x) & \
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STATUS_COMMAND_RESPONSE_READY_MASK) >> \
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STATUS_COMMAND_RESPONSE_READY_OFFSET)
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// CMD_REQ Register
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#define CMD_STATUS 0x400
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#define CMD_PARAM 0x438
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#define CMD_REQ 0x43C
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#define CMD_PARAM_OFFSET 0x4
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#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29)
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#define CMD_TARGET_IP_TYPE_OFFSET 29
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#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24)
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#define CMD_TARGET_IP_INSTANCE_ID_OFFSET 24
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#define CMD_TYPE_MASK GENMASK(23, 16)
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#define CMD_TYPE_OFFSET 16
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#define CMD_OPCODE_MASK GENMASK(15, 0)
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#define CMD_OPCODE_OFFSET 0
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#define CMD_INIT 0
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#define OPCODE_GET_MEM_INTF_INFO 0x0001
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#define OPCODE_GET_MEM_TECHNOLOGY 0x0002
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#define OPCODE_GET_MEM_WIDTH_INFO 0x0004
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#define OPCODE_TRIG_MEM_CAL 0x000A
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#define OPCODE_ECC_ENABLE_STATUS 0x0102
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#define OPCODE_ECC_INTERRUPT_MASK 0x0105
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#define OPCODE_ECC_SCRUB_MODE_0_START 0x0202
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#define OPCODE_ECC_SCRUB_MODE_1_START 0x0203
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#define OPCODE_BIST_RESULTS_STATUS 0x0302
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#define OPCODE_BIST_MEM_INIT_START 0x0303
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// Please update according to IOSSM mailbox spec
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#define MBOX_ID_IOSSM 0x00
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#define MBOX_CMD_GET_SYS_INFO 0x01
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// Please update according to IOSSM mailbox spec
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#define MBOX_CMD_GET_MEM_INFO 0x02
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#define MBOX_CMD_TRIG_CONTROLLER_OP 0x04
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#define MBOX_CMD_TRIG_MEM_CAL_OP 0x05
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#define MBOX_CMD_POKE_REG 0xFD
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#define MBOX_CMD_PEEK_REG 0xFE
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#define MBOX_CMD_GET_DEBUG_LOG 0xFF
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// Please update according to IOSSM mailbox spec
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#define MBOX_CMD_DIRECT 0x00
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0_MASK 0x01
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#define IOSSM_MB_WRITE(addr, data) mmio_write_32(addr, data)
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/* DDR4 Register */
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#define DDR4_PWRCTL_OFFSET 0x30
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#define DDR4_SBRCTL_OFFSET 0x0F24
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#define DDR4_SBRSTAT_OFFSET 0x0F28
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#define DDR4_SBRWDATA0_OFFSET 0x0F2C
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#define DDR4_SBRSTART0_OFFSET 0x0F38
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#define DDR4_SBRWDATA1_OFFSET 0x0F30
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#define DDR4_SBRSTART1_OFFSET 0x0F3C
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#define DDR4_SBRRANGE0_OFFSET 0x0F40
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#define DDR4_SBRRANGE1_OFFSET 0x0F44
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#define DDR4_ECCCFG0_OFFSET 0x70
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#define DDR4_ECCCFG1_OFFSET 0x74
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#define DDR4_PCTRL0_OFFSET 0x0490
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#define LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT 30
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#define ALL_PROTECTED 0x7F
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#define LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT 8
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#define LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK BIT(4)
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#define DDR4_PCTRL0_PORT_EN BIT(0)
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#define DDR4_SBRCTL_SCRUB_EN BIT(0)
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#define DDR4_SBRSTAT_SCRUB_BUSY BIT(0)
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#define DDR4_SBRCTL_SCRUB_BURST_1 BIT(4)
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#define DDR4_SBRCTL_SCRUB_WRITE BIT(2)
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#define DDR4_SBRSTAT_SCRUB_DONE BIT(1)
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/* FUNCTION DEFINATION */
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int ddr_calibration_check(void);
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int iossm_mb_init(void);
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int iossm_mb_read_response(void);
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int iossm_mb_send(uint32_t cmd_target_ip_type, uint32_t cmd_target_ip_instance_id,
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uint32_t cmd_type, uint32_t cmd_opcode, uint32_t *args,
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unsigned int len);
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int ddr_iossm_mailbox_cmd(uint32_t cmd);
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int ddr_init(void);
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int ddr_config_handoff(handoff *hoff_ptr);
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void ddr_enable_ns_access(void);
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void ddr_enable_firewall(void);
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bool is_ddr_init_in_progress(void);
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int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
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int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
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int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms);
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#endif
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