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https://github.com/ARM-software/arm-trusted-firmware.git
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a4c394561a
Previously the SCR_EL3.AMVOFFEN bit was set for all contexts, this behavior is incorrect as it allows secure world to access the virtual offset registers when it should not be able to. This patch only sets AMVOFFEN for non-secure world. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I2c61fe0a8a0092df089f1cb2c0d8a45c8c8ad0d3
655 lines
16 KiB
C
655 lines
16 KiB
C
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <cdefs.h>
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#include <inttypes.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "../amu_private.h"
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/pubsub_events.h>
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#include <lib/extensions/amu.h>
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#include <plat/common/platform.h>
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#if ENABLE_AMU_FCONF
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# include <lib/fconf/fconf.h>
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# include <lib/fconf/fconf_amu_getter.h>
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#endif
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#if ENABLE_MPMM
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# include <lib/mpmm/mpmm.h>
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#endif
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS];
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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uint64_t group1_cnts[AMU_GROUP1_MAX_COUNTERS];
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#endif
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/* Architected event counter 1 does not have an offset register */
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uint64_t group0_voffsets[AMU_GROUP0_MAX_COUNTERS - 1U];
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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uint64_t group1_voffsets[AMU_GROUP1_MAX_COUNTERS];
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#endif
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uint16_t group0_enable;
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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uint16_t group1_enable;
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#endif
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};
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static struct amu_ctx amu_ctxs_[PLATFORM_CORE_COUNT];
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CASSERT((sizeof(amu_ctxs_[0].group0_enable) * CHAR_BIT) <= AMU_GROUP0_MAX_COUNTERS,
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amu_ctx_group0_enable_cannot_represent_all_group0_counters);
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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CASSERT((sizeof(amu_ctxs_[0].group1_enable) * CHAR_BIT) <= AMU_GROUP1_MAX_COUNTERS,
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amu_ctx_group1_enable_cannot_represent_all_group1_counters);
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#endif
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static inline __unused uint64_t read_id_aa64pfr0_el1_amu(void)
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{
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return (read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
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ID_AA64PFR0_AMU_MASK;
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}
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static inline __unused uint64_t read_hcr_el2_amvoffen(void)
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{
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return (read_hcr_el2() & HCR_AMVOFFEN_BIT) >>
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HCR_AMVOFFEN_SHIFT;
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}
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static inline __unused void write_cptr_el2_tam(uint64_t value)
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{
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write_cptr_el2((read_cptr_el2() & ~CPTR_EL2_TAM_BIT) |
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((value << CPTR_EL2_TAM_SHIFT) & CPTR_EL2_TAM_BIT));
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}
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static inline __unused void ctx_write_cptr_el3_tam(cpu_context_t *ctx, uint64_t tam)
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{
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uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
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value &= ~TAM_BIT;
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value |= (tam << TAM_SHIFT) & TAM_BIT;
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write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, value);
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}
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static inline __unused void ctx_write_scr_el3_amvoffen(cpu_context_t *ctx, uint64_t amvoffen)
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{
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uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
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value &= ~SCR_AMVOFFEN_BIT;
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value |= (amvoffen << SCR_AMVOFFEN_SHIFT) & SCR_AMVOFFEN_BIT;
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write_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3, value);
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}
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static inline __unused void write_hcr_el2_amvoffen(uint64_t value)
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{
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write_hcr_el2((read_hcr_el2() & ~HCR_AMVOFFEN_BIT) |
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((value << HCR_AMVOFFEN_SHIFT) & HCR_AMVOFFEN_BIT));
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}
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static inline __unused void write_amcr_el0_cg1rz(uint64_t value)
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{
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write_amcr_el0((read_amcr_el0() & ~AMCR_CG1RZ_BIT) |
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((value << AMCR_CG1RZ_SHIFT) & AMCR_CG1RZ_BIT));
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}
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static inline __unused uint64_t read_amcfgr_el0_ncg(void)
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{
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return (read_amcfgr_el0() >> AMCFGR_EL0_NCG_SHIFT) &
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AMCFGR_EL0_NCG_MASK;
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}
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static inline __unused uint64_t read_amcgcr_el0_cg0nc(void)
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{
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return (read_amcgcr_el0() >> AMCGCR_EL0_CG0NC_SHIFT) &
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AMCGCR_EL0_CG0NC_MASK;
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}
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static inline __unused uint64_t read_amcg1idr_el0_voff(void)
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{
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return (read_amcg1idr_el0() >> AMCG1IDR_VOFF_SHIFT) &
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AMCG1IDR_VOFF_MASK;
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}
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static inline __unused uint64_t read_amcgcr_el0_cg1nc(void)
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{
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return (read_amcgcr_el0() >> AMCGCR_EL0_CG1NC_SHIFT) &
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AMCGCR_EL0_CG1NC_MASK;
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}
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static inline __unused uint64_t read_amcntenset0_el0_px(void)
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{
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return (read_amcntenset0_el0() >> AMCNTENSET0_EL0_Pn_SHIFT) &
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AMCNTENSET0_EL0_Pn_MASK;
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}
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static inline __unused uint64_t read_amcntenset1_el0_px(void)
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{
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return (read_amcntenset1_el0() >> AMCNTENSET1_EL0_Pn_SHIFT) &
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AMCNTENSET1_EL0_Pn_MASK;
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}
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static inline __unused void write_amcntenset0_el0_px(uint64_t px)
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{
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uint64_t value = read_amcntenset0_el0();
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value &= ~AMCNTENSET0_EL0_Pn_MASK;
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value |= (px << AMCNTENSET0_EL0_Pn_SHIFT) & AMCNTENSET0_EL0_Pn_MASK;
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write_amcntenset0_el0(value);
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}
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static inline __unused void write_amcntenset1_el0_px(uint64_t px)
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{
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uint64_t value = read_amcntenset1_el0();
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value &= ~AMCNTENSET1_EL0_Pn_MASK;
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value |= (px << AMCNTENSET1_EL0_Pn_SHIFT) & AMCNTENSET1_EL0_Pn_MASK;
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write_amcntenset1_el0(value);
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}
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static inline __unused void write_amcntenclr0_el0_px(uint64_t px)
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{
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uint64_t value = read_amcntenclr0_el0();
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value &= ~AMCNTENCLR0_EL0_Pn_MASK;
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value |= (px << AMCNTENCLR0_EL0_Pn_SHIFT) & AMCNTENCLR0_EL0_Pn_MASK;
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write_amcntenclr0_el0(value);
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}
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static inline __unused void write_amcntenclr1_el0_px(uint64_t px)
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{
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uint64_t value = read_amcntenclr1_el0();
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value &= ~AMCNTENCLR1_EL0_Pn_MASK;
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value |= (px << AMCNTENCLR1_EL0_Pn_SHIFT) & AMCNTENCLR1_EL0_Pn_MASK;
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write_amcntenclr1_el0(value);
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}
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static __unused bool amu_supported(void)
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{
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return read_id_aa64pfr0_el1_amu() >= ID_AA64PFR0_AMU_V1;
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}
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static __unused bool amu_v1p1_supported(void)
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{
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return read_id_aa64pfr0_el1_amu() >= ID_AA64PFR0_AMU_V1P1;
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}
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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static __unused bool amu_group1_supported(void)
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{
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return read_amcfgr_el0_ncg() > 0U;
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}
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#endif
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/*
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* Enable counters. This function is meant to be invoked by the context
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* management library before exiting from EL3.
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*/
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void amu_enable(bool el2_unused, cpu_context_t *ctx)
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{
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uint64_t id_aa64pfr0_el1_amu; /* AMU version */
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uint64_t amcfgr_el0_ncg; /* Number of counter groups */
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uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */
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uint64_t amcntenset0_el0_px = 0x0; /* Group 0 enable mask */
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uint64_t amcntenset1_el0_px = 0x0; /* Group 1 enable mask */
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id_aa64pfr0_el1_amu = read_id_aa64pfr0_el1_amu();
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if (id_aa64pfr0_el1_amu == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
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/*
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* If the AMU is unsupported, nothing needs to be done.
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*/
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return;
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}
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if (el2_unused) {
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/*
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* CPTR_EL2.TAM: Set to zero so any accesses to the Activity
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* Monitor registers do not trap to EL2.
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*/
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write_cptr_el2_tam(0U);
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}
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/*
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* Retrieve and update the CPTR_EL3 value from the context mentioned
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* in 'ctx'. Set CPTR_EL3.TAM to zero so that any accesses to
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* the Activity Monitor registers do not trap to EL3.
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*/
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ctx_write_cptr_el3_tam(ctx, 0U);
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/*
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* Retrieve the number of architected counters. All of these counters
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* are enabled by default.
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*/
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amcgcr_el0_cg0nc = read_amcgcr_el0_cg0nc();
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amcntenset0_el0_px = (UINT64_C(1) << (amcgcr_el0_cg0nc)) - 1U;
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assert(amcgcr_el0_cg0nc <= AMU_AMCGCR_CG0NC_MAX);
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/*
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* The platform may opt to enable specific auxiliary counters. This can
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* be done via the common FCONF getter, or via the platform-implemented
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* function.
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*/
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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const struct amu_topology *topology;
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#if ENABLE_AMU_FCONF
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topology = FCONF_GET_PROPERTY(amu, config, topology);
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#else
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topology = plat_amu_topology();
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#endif /* ENABLE_AMU_FCONF */
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if (topology != NULL) {
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unsigned int core_pos = plat_my_core_pos();
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amcntenset1_el0_px = topology->cores[core_pos].enable;
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} else {
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ERROR("AMU: failed to generate AMU topology\n");
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}
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#endif /* ENABLE_AMU_AUXILIARY_COUNTERS */
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/*
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* Enable the requested counters.
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*/
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write_amcntenset0_el0_px(amcntenset0_el0_px);
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amcfgr_el0_ncg = read_amcfgr_el0_ncg();
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if (amcfgr_el0_ncg > 0U) {
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write_amcntenset1_el0_px(amcntenset1_el0_px);
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#if !ENABLE_AMU_AUXILIARY_COUNTERS
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VERBOSE("AMU: auxiliary counters detected but support is disabled\n");
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#endif
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}
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/* Initialize FEAT_AMUv1p1 features if present. */
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if (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) {
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if (el2_unused) {
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/*
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* Make sure virtual offsets are disabled if EL2 not
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* used.
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*/
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write_hcr_el2_amvoffen(0U);
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} else {
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/*
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* Virtual offset registers are only accessible from EL3
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* and EL2, when clear, this bit traps accesses from EL2
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* so we set it to 1 when EL2 is present.
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*/
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ctx_write_scr_el3_amvoffen(ctx, 1U);
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}
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#if AMU_RESTRICT_COUNTERS
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/*
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* FEAT_AMUv1p1 adds a register field to restrict access to
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* group 1 counters at all but the highest implemented EL. This
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* is controlled with the `AMU_RESTRICT_COUNTERS` compile time
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* flag, when set, system register reads at lower ELs return
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* zero. Reads from the memory mapped view are unaffected.
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*/
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VERBOSE("AMU group 1 counter access restricted.\n");
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write_amcr_el0_cg1rz(1U);
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#else
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write_amcr_el0_cg1rz(0U);
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#endif
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}
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#if ENABLE_MPMM
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mpmm_enable();
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#endif
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}
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/* Read the group 0 counter identified by the given `idx`. */
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static uint64_t amu_group0_cnt_read(unsigned int idx)
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{
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assert(amu_supported());
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assert(idx < read_amcgcr_el0_cg0nc());
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return amu_group0_cnt_read_internal(idx);
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}
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/* Write the group 0 counter identified by the given `idx` with `val` */
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static void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(idx < read_amcgcr_el0_cg0nc());
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amu_group0_cnt_write_internal(idx, val);
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isb();
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}
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/*
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* Unlike with auxiliary counters, we cannot detect at runtime whether an
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* architected counter supports a virtual offset. These are instead fixed
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* according to FEAT_AMUv1p1, but this switch will need to be updated if later
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* revisions of FEAT_AMU add additional architected counters.
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*/
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static bool amu_group0_voffset_supported(uint64_t idx)
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{
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switch (idx) {
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case 0U:
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case 2U:
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case 3U:
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return true;
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case 1U:
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return false;
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default:
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ERROR("AMU: can't set up virtual offset for unknown "
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"architected counter %" PRIu64 "!\n", idx);
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panic();
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}
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}
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/*
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* Read the group 0 offset register for a given index. Index must be 0, 2,
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* or 3, the register for 1 does not exist.
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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static uint64_t amu_group0_voffset_read(unsigned int idx)
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{
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assert(amu_v1p1_supported());
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assert(idx < read_amcgcr_el0_cg0nc());
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assert(idx != 1U);
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return amu_group0_voffset_read_internal(idx);
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}
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/*
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* Write the group 0 offset register for a given index. Index must be 0, 2, or
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* 3, the register for 1 does not exist.
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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static void amu_group0_voffset_write(unsigned int idx, uint64_t val)
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{
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assert(amu_v1p1_supported());
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assert(idx < read_amcgcr_el0_cg0nc());
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assert(idx != 1U);
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amu_group0_voffset_write_internal(idx, val);
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isb();
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}
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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/* Read the group 1 counter identified by the given `idx` */
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static uint64_t amu_group1_cnt_read(unsigned int idx)
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{
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assert(amu_supported());
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assert(amu_group1_supported());
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assert(idx < read_amcgcr_el0_cg1nc());
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return amu_group1_cnt_read_internal(idx);
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}
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/* Write the group 1 counter identified by the given `idx` with `val` */
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static void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(amu_group1_supported());
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assert(idx < read_amcgcr_el0_cg1nc());
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amu_group1_cnt_write_internal(idx, val);
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isb();
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}
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/*
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* Read the group 1 offset register for a given index.
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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static uint64_t amu_group1_voffset_read(unsigned int idx)
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{
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assert(amu_v1p1_supported());
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assert(amu_group1_supported());
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assert(idx < read_amcgcr_el0_cg1nc());
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assert((read_amcg1idr_el0_voff() & (UINT64_C(1) << idx)) != 0U);
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return amu_group1_voffset_read_internal(idx);
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}
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/*
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* Write the group 1 offset register for a given index.
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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static void amu_group1_voffset_write(unsigned int idx, uint64_t val)
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{
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assert(amu_v1p1_supported());
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assert(amu_group1_supported());
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assert(idx < read_amcgcr_el0_cg1nc());
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assert((read_amcg1idr_el0_voff() & (UINT64_C(1) << idx)) != 0U);
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amu_group1_voffset_write_internal(idx, val);
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isb();
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}
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#endif
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static void *amu_context_save(const void *arg)
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{
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uint64_t i, j;
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unsigned int core_pos;
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struct amu_ctx *ctx;
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uint64_t id_aa64pfr0_el1_amu; /* AMU version */
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uint64_t hcr_el2_amvoffen; /* AMU virtual offsets enabled */
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uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
uint64_t amcg1idr_el0_voff; /* Auxiliary counters with virtual offsets */
|
|
uint64_t amcfgr_el0_ncg; /* Number of counter groups */
|
|
uint64_t amcgcr_el0_cg1nc; /* Number of group 1 counters */
|
|
#endif
|
|
|
|
id_aa64pfr0_el1_amu = read_id_aa64pfr0_el1_amu();
|
|
if (id_aa64pfr0_el1_amu == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
|
|
return (void *)0;
|
|
}
|
|
|
|
core_pos = plat_my_core_pos();
|
|
ctx = &amu_ctxs_[core_pos];
|
|
|
|
amcgcr_el0_cg0nc = read_amcgcr_el0_cg0nc();
|
|
hcr_el2_amvoffen = (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) ?
|
|
read_hcr_el2_amvoffen() : 0U;
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
amcfgr_el0_ncg = read_amcfgr_el0_ncg();
|
|
amcgcr_el0_cg1nc = (amcfgr_el0_ncg > 0U) ? read_amcgcr_el0_cg1nc() : 0U;
|
|
amcg1idr_el0_voff = (hcr_el2_amvoffen != 0U) ? read_amcg1idr_el0_voff() : 0U;
|
|
#endif
|
|
|
|
/*
|
|
* Disable all AMU counters.
|
|
*/
|
|
|
|
ctx->group0_enable = read_amcntenset0_el0_px();
|
|
write_amcntenclr0_el0_px(ctx->group0_enable);
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
if (amcfgr_el0_ncg > 0U) {
|
|
ctx->group1_enable = read_amcntenset1_el0_px();
|
|
write_amcntenclr1_el0_px(ctx->group1_enable);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Save the counters to the local context.
|
|
*/
|
|
|
|
isb(); /* Ensure counters have been stopped */
|
|
|
|
for (i = 0U; i < amcgcr_el0_cg0nc; i++) {
|
|
ctx->group0_cnts[i] = amu_group0_cnt_read(i);
|
|
}
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
for (i = 0U; i < amcgcr_el0_cg1nc; i++) {
|
|
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Save virtual offsets for counters that offer them.
|
|
*/
|
|
|
|
if (hcr_el2_amvoffen != 0U) {
|
|
for (i = 0U, j = 0U; i < amcgcr_el0_cg0nc; i++) {
|
|
if (!amu_group0_voffset_supported(i)) {
|
|
continue; /* No virtual offset */
|
|
}
|
|
|
|
ctx->group0_voffsets[j++] = amu_group0_voffset_read(i);
|
|
}
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
for (i = 0U, j = 0U; i < amcgcr_el0_cg1nc; i++) {
|
|
if ((amcg1idr_el0_voff >> i) & 1U) {
|
|
continue; /* No virtual offset */
|
|
}
|
|
|
|
ctx->group1_voffsets[j++] = amu_group1_voffset_read(i);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return (void *)0;
|
|
}
|
|
|
|
static void *amu_context_restore(const void *arg)
|
|
{
|
|
uint64_t i, j;
|
|
|
|
unsigned int core_pos;
|
|
struct amu_ctx *ctx;
|
|
|
|
uint64_t id_aa64pfr0_el1_amu; /* AMU version */
|
|
|
|
uint64_t hcr_el2_amvoffen; /* AMU virtual offsets enabled */
|
|
|
|
uint64_t amcfgr_el0_ncg; /* Number of counter groups */
|
|
uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
uint64_t amcgcr_el0_cg1nc; /* Number of group 1 counters */
|
|
uint64_t amcg1idr_el0_voff; /* Auxiliary counters with virtual offsets */
|
|
#endif
|
|
|
|
id_aa64pfr0_el1_amu = read_id_aa64pfr0_el1_amu();
|
|
if (id_aa64pfr0_el1_amu == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
|
|
return (void *)0;
|
|
}
|
|
|
|
core_pos = plat_my_core_pos();
|
|
ctx = &amu_ctxs_[core_pos];
|
|
|
|
amcfgr_el0_ncg = read_amcfgr_el0_ncg();
|
|
amcgcr_el0_cg0nc = read_amcgcr_el0_cg0nc();
|
|
|
|
hcr_el2_amvoffen = (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) ?
|
|
read_hcr_el2_amvoffen() : 0U;
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
amcgcr_el0_cg1nc = (amcfgr_el0_ncg > 0U) ? read_amcgcr_el0_cg1nc() : 0U;
|
|
amcg1idr_el0_voff = (hcr_el2_amvoffen != 0U) ? read_amcg1idr_el0_voff() : 0U;
|
|
#endif
|
|
|
|
/*
|
|
* Sanity check that all counters were disabled when the context was
|
|
* previously saved.
|
|
*/
|
|
|
|
assert(read_amcntenset0_el0_px() == 0U);
|
|
|
|
if (amcfgr_el0_ncg > 0U) {
|
|
assert(read_amcntenset1_el0_px() == 0U);
|
|
}
|
|
|
|
/*
|
|
* Restore the counter values from the local context.
|
|
*/
|
|
|
|
for (i = 0U; i < amcgcr_el0_cg0nc; i++) {
|
|
amu_group0_cnt_write(i, ctx->group0_cnts[i]);
|
|
}
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
for (i = 0U; i < amcgcr_el0_cg1nc; i++) {
|
|
amu_group1_cnt_write(i, ctx->group1_cnts[i]);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Restore virtual offsets for counters that offer them.
|
|
*/
|
|
|
|
if (hcr_el2_amvoffen != 0U) {
|
|
for (i = 0U, j = 0U; i < amcgcr_el0_cg0nc; i++) {
|
|
if (!amu_group0_voffset_supported(i)) {
|
|
continue; /* No virtual offset */
|
|
}
|
|
|
|
amu_group0_voffset_write(i, ctx->group0_voffsets[j++]);
|
|
}
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
for (i = 0U, j = 0U; i < amcgcr_el0_cg1nc; i++) {
|
|
if ((amcg1idr_el0_voff >> i) & 1U) {
|
|
continue; /* No virtual offset */
|
|
}
|
|
|
|
amu_group1_voffset_write(i, ctx->group1_voffsets[j++]);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Re-enable counters that were disabled during context save.
|
|
*/
|
|
|
|
write_amcntenset0_el0_px(ctx->group0_enable);
|
|
|
|
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
|
if (amcfgr_el0_ncg > 0) {
|
|
write_amcntenset1_el0_px(ctx->group1_enable);
|
|
}
|
|
#endif
|
|
|
|
#if ENABLE_MPMM
|
|
mpmm_enable();
|
|
#endif
|
|
|
|
return (void *)0;
|
|
}
|
|
|
|
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);
|
|
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, amu_context_restore);
|