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With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on each other. The enable code relies on the register being initialised to zero and omits to reset NSPBE. However, this is not obvious. Reset the bit explicitly to document this. Similarly, reset the STE bit , since it's part of the feature enablement. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
24 lines
408 B
C
24 lines
408 B
C
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/extensions/trf.h>
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void trf_init_el3(void)
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{
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uint32_t val;
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/*
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* Allow access of trace filter control registers from
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* non-monitor mode.
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*/
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val = read_sdcr();
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val &= ~(SDCR_TTRF_BIT);
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write_sdcr(val);
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}
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