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https://github.com/ARM-software/arm-trusted-firmware.git
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bb9b89366f
TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA so refactor the code to manage it accordingly. Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7 Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
113 lines
2.4 KiB
Text
113 lines
2.4 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <platform_def.h>
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#define MHU_TX_ADDR 46040000 /* hex */
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#define MHU_RX_ADDR 46140000 /* hex */
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#define RSE_MHU_TX_ADDR 49010000 /* hex */
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#define RSE_MHU_RX_ADDR 49110000 /* hex */
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#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
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#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
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#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
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#define ETHERNET_ADDR 18000000
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#define ETHERNET_INT 109
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#define SYS_REGS_ADDR 1c010000
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#define MMC_ADDR 1c050000
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#define MMC_INT_0 107
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#define MMC_INT_1 108
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#define RTC_ADDR 1c170000
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#define RTC_INT 100
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#define KMI_0_ADDR 1c060000
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#define KMI_0_INT 197
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#define KMI_1_ADDR 1c070000
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#define KMI_1_INT 103
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#define VIRTIO_BLOCK_ADDR 1c130000
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#define VIRTIO_BLOCK_INT 204
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#if TARGET_FLAVOUR_FPGA
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#define DPU_ADDR 2cc00000
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#define DPU_IRQ 69
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#endif
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#include "tc-common.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc-fvp.dtsi"
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#else
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#include "tc-fpga.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc3-4-base.dtsi"
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/ {
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/*
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* The kaslr-seed node is a placeholder in DT. In the booting
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* sequence, it will be initialized in U-Boot and then later
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* used by Linux kernel.
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*/
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chosen {
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kaslr-seed = <0x0 0x0>;
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};
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spe-pmu-mid {
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status = "okay";
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};
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spe-pmu-big {
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status = "okay";
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};
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ni-pmu {
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compatible = "arm,ni-tower";
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reg = <0x0 0x4f000000 0x0 0x4000000>;
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};
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#if TARGET_FLAVOUR_FVP
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smmu_700: iommu@3f000000 {
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status = "okay";
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};
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smmu_700_dpu: iommu@4002a00000 {
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status = "okay";
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};
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#else
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smmu_600: smmu@2ce00000 {
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status = "okay";
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};
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#endif
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dp0: display@DPU_ADDR {
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#if TARGET_FLAVOUR_FVP
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iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
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<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
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#else /* TARGET_FLAVOUR_FPGA */
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iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
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<&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
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<&smmu_600 8>, <&smmu_600 9>;
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#endif
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};
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gpu: gpu@2d000000 {
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "JOB", "MMU", "GPU";
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#if TARGET_FLAVOUR_FVP
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iommus = <&smmu_700 0x200>;
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#endif
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};
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};
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