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967999d0d9
This node specifies the location of the MPAM registers for the DSU. Rename the node to clarify this. Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com> Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4
140 lines
2.9 KiB
Text
140 lines
2.9 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define LIT_CAPACITY 239
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#define MID_CAPACITY 686
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#define BIG_CAPACITY 1024
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#define MHU_TX_COMPAT "arm,mhuv3"
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#define MHU_TX_INT_NAME ""
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#define MHU_RX_COMPAT "arm,mhuv3"
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#define MHU_OFFSET 0x10000
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#define MHU_MBOX_CELLS 3
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#define MHU_RX_INT_NUM 300
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#define MHU_RX_INT_NAME "combined"
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#define DSU_MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#if TARGET_FLAVOUR_FVP
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#define DPU_ADDR 4000000000
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#define DPU_IRQ 579
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#endif
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#include "tc-base.dtsi"
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/ {
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cpus {
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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};
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rse_mbox_db_rx: mhu@RSE_MHU_RX_ADDR {
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compatible = MHU_RX_COMPAT;
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reg = <0x0 ADDRESSIFY(RSE_MHU_RX_ADDR) 0x0 MHU_OFFSET>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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#mbox-cells = <MHU_MBOX_CELLS>;
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interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = MHU_RX_INT_NAME;
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#if TARGET_FLAVOUR_FPGA
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status = "disabled";
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#endif
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};
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rse_mbox_db_tx: mhu@RSE_MHU_TX_ADDR {
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compatible = MHU_TX_COMPAT;
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reg = <0x0 ADDRESSIFY(RSE_MHU_TX_ADDR) 0x0 MHU_OFFSET>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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#mbox-cells = <MHU_MBOX_CELLS>;
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interrupt-names = MHU_TX_INT_NAME;
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#if TARGET_FLAVOUR_FPGA
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status = "disabled";
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#endif
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};
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gic: interrupt-controller@GIC_CTRL_ADDR {
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ppi-partitions {
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ppi_partition_little: interrupt-partition-0 {
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affinity = <&CPU0>, <&CPU1>;
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};
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ppi_partition_mid: interrupt-partition-1 {
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affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
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};
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ppi_partition_big: interrupt-partition-2 {
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affinity = <&CPU6>, <&CPU7>;
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};
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};
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};
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sram: sram@6000000 {
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cpu_scp_scmi_p2a: scp-shmem@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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};
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firmware {
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scmi {
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mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
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shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
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};
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rse {
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compatible = "arm,rse";
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mbox-names = "tx", "rx";
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mboxes = <&rse_mbox_db_tx 0 0 0>, <&rse_mbox_db_rx 0 0 0>;
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#if TARGET_FLAVOUR_FPGA
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status = "disabled";
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#endif
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};
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};
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dsu-pmu {
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compatible = "arm,dsu-pmu";
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cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
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};
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cs-pmu@0 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
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};
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cs-pmu@1 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
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};
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cs-pmu@2 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
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};
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cs-pmu@3 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
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};
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};
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