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20544d66cc
For ST STM32MP15 boards, where the default BL32 is OP-TEE, we add new versions of DT files with -sp_min.dts extension to manage this configuration. These files can be compiled directly, or, with the previous patch, the same command line can be used and those sp_min files will be automatically used, if AARCH32_SP=sp_min option is used. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I5aabe415b0302da48f02918a3dbd24f334eb8e7d
69 lines
1.1 KiB
Text
69 lines
1.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
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*/
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#include "stm32mp157c-dk2.dts"
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/ {
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model = "STMicroelectronics STM32MP157C-DK2 Discovery Board (SP_MIN)";
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};
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_PLL4P
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_CSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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st,clkdiv = <
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DIV(DIV_MPU, 1)
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DIV(DIV_AXI, 0)
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DIV(DIV_MCU, 0)
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DIV(DIV_APB1, 1)
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DIV(DIV_APB2, 1)
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DIV(DIV_APB3, 1)
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DIV(DIV_APB4, 1)
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DIV(DIV_APB5, 2)
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DIV(DIV_MCO1, 0)
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DIV(DIV_MCO2, 0)
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>;
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};
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