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98c6516520
Cortex-A320 has been announced, rename arcadia to Cortex-A320. Ref: https://newsroom.arm.com/blog/introducing-arm-cortex-a320-cpu https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a320 Change-Id: Ifb3743d43dca3d8caaf1e7416715ccca4fdf195f Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
67 lines
1.9 KiB
ArmAsm
67 lines
1.9 KiB
ArmAsm
/*
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* Copyright (c) 2024-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a320.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A320 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A320 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue cortex_a320
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cpu_reset_func_start cortex_a320
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/* Disable speculative loads */
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msr SSBS, xzr
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enable_mpmm
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cpu_reset_func_end cortex_a320
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a320_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A320_CPUPWRCTLR_EL1, CORTEX_A320_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_a320_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-A320 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a320_regs, "aS"
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cortex_a320_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a320_cpu_reg_dump
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adr x6, cortex_a320_regs
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mrs x8, CORTEX_A320_CPUECTLR_EL1
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ret
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endfunc cortex_a320_cpu_reg_dump
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declare_cpu_ops cortex_a320, CORTEX_A320_MIDR, \
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cortex_a320_reset_func, \
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cortex_a320_core_pwr_dwn
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