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chore: rename arcadia to Cortex-A320

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Cortex-A320 has been announced, rename arcadia to Cortex-A320.

Ref:
https://newsroom.arm.com/blog/introducing-arm-cortex-a320-cpu
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a320

Change-Id: Ifb3743d43dca3d8caaf1e7416715ccca4fdf195f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2025-02-26 10:46:50 -06:00
parent bac623d186
commit 98c6516520
3 changed files with 31 additions and 32 deletions
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18
include/lib/cpus/aarch64/cortex_arcadia.h → include/lib/cpus/aarch64/cortex_a320.h
View file

@ -1,24 +1,24 @@
/*
* Copyright (c) 2024, Arm Limited. All rights reserved.
* Copyright (c) 2024-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_ARCADIA_H
#define CORTEX_ARCADIA_H
#ifndef CORTEX_A320_H
#define CORTEX_A320_H
#define CORTEX_ARCADIA_MIDR U(0x410FD8F0)
#define CORTEX_A320_MIDR U(0x410FD8F0)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_ARCADIA_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_ARCADIA_CPUECTLR_EL1_EXTLLC_BIT U(0)
#define CORTEX_A320_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A320_CPUECTLR_EL1_EXTLLC_BIT U(0)
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_ARCADIA_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#define CORTEX_A320_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A320_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_ARCADIA_H */
#endif /* CORTEX_A320_H */

38
lib/cpus/aarch64/cortex_arcadia.S → lib/cpus/aarch64/cortex_a320.S
View file

@ -7,44 +7,44 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_arcadia.h>
#include <cortex_a320.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-ARCADIA must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Cortex-A320 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex-ARCADIA supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Cortex-A320 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
cpu_reset_prologue cortex_arcadia
cpu_reset_prologue cortex_a320
cpu_reset_func_start cortex_arcadia
cpu_reset_func_start cortex_a320
/* Disable speculative loads */
msr SSBS, xzr
enable_mpmm
cpu_reset_func_end cortex_arcadia
cpu_reset_func_end cortex_a320
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_arcadia_core_pwr_dwn
func cortex_a320_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set CORTEX_ARCADIA_CPUPWRCTLR_EL1, CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
sysreg_bit_set CORTEX_A320_CPUPWRCTLR_EL1, CORTEX_A320_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_arcadia_core_pwr_dwn
endfunc cortex_a320_core_pwr_dwn
/* ---------------------------------------------
* This function provides Cortex-Arcadia specific
* This function provides Cortex-A320 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@ -52,16 +52,16 @@ endfunc cortex_arcadia_core_pwr_dwn
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_arcadia_regs, "aS"
cortex_arcadia_regs: /* The ascii list of register names to be reported */
.section .rodata.cortex_a320_regs, "aS"
cortex_a320_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_arcadia_cpu_reg_dump
adr x6, cortex_arcadia_regs
mrs x8, CORTEX_ARCADIA_CPUECTLR_EL1
func cortex_a320_cpu_reg_dump
adr x6, cortex_a320_regs
mrs x8, CORTEX_A320_CPUECTLR_EL1
ret
endfunc cortex_arcadia_cpu_reg_dump
endfunc cortex_a320_cpu_reg_dump
declare_cpu_ops cortex_arcadia, CORTEX_ARCADIA_MIDR, \
cortex_arcadia_reset_func, \
cortex_arcadia_core_pwr_dwn
declare_cpu_ops cortex_a320, CORTEX_A320_MIDR, \
cortex_a320_reset_func, \
cortex_a320_core_pwr_dwn

7
plat/arm/board/fvp/platform.mk
View file

@ -225,7 +225,8 @@ endif
#Include all CPUs to build to support all-errata build.
ifeq (${ENABLE_ERRATA_ALL},1)
BUILD_CPUS_WITH_NO_FVP_MODEL = 1
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \
lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_a725.S \
lib/cpus/aarch64/cortex_x1.S \
@ -241,11 +242,9 @@ ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
# travis/gelas need these
FEAT_PABANDON := 1
ERRATA_SME_POWER_DOWN := 1
FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
lib/cpus/aarch64/cortex_gelas.S \
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
lib/cpus/aarch64/travis.S \
lib/cpus/aarch64/cortex_arcadia.S \
lib/cpus/aarch64/cortex_alto.S
endif