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7f152ea685
Apply the mitigation only for the revision and variant mentioned in the SDEN. SDEN Documentation: https://developer.arm.com/documentation/SDEN859515/latest Change-Id: Ifda1f4cb32bdec9a9af29397ddc03bf22a7a87fc Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
60 lines
2 KiB
C
60 lines
2 KiB
C
/*
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* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A75_H
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#define CORTEX_A75_H
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#include <lib/utils_def.h>
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/* Cortex-A75 MIDR */
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#define CORTEX_A75_MIDR U(0x410fd0a0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35)
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/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
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#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1)
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#define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4)
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/*
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* The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are
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* fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are
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* programmable by programming the appropriate Event count bits in
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* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
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* enable this with suitable programming.
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*/
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#define CORTEX_A75_AMU_NR_COUNTERS U(5)
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#define CORTEX_A75_AMU_GROUP0_MASK U(0x7)
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#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3)
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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uint64_t cortex_a75_amu_cnt_read(int idx);
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void cortex_a75_amu_cnt_write(int idx, uint64_t val);
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unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void);
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unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
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void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
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void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
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#if ERRATA_A75_764081
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long check_erratum_cortex_a75_764081(long cpu_rev);
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#endif /* ERRATA_A75_764081 */
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A75_H */
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