Sieu Mun Tang 94a546acc4 feat(intel): pinmux and power manager config for Agilex5 platform ... Read the hand-off data and configure the pinmux select, IO control, IO delay and use FPGA switch. Configure the power manager PSS SRAM power gate. Change-Id: I2241018cbf2828182e8af84ddb214ce57e9f242a Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>		2024-10-24 15:23:43 +08:00
..
agilex	Merge "fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset" into integration	2024-10-22 17:30:32 +02:00
agilex5	feat(intel): pinmux and power manager config for Agilex5 platform	2024-10-24 15:23:43 +08:00
common	Merge "fix(intel): fix CCU for cache maintenance" into integration	2024-10-22 17:33:08 +02:00
n5x	fix(intel): update preloaded_bl33_base for legacy product	2024-10-22 09:32:37 +08:00
stratix10	Merge "fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset" into integration	2024-10-22 17:30:32 +02:00