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![]() If the interrupt being targeted is released from the CPU before the CLEAR command is sent to the CPU then a subsequent SET command may not be delivered in a finite time. To workaround this, issue an unblocking event by toggling GICR_CTLR.DPG* bits after clearing the cpu group enable (EnableGrp* bits of GIC CPU interface register) This fix is implemented as per the errata 2384374-part 2 workaround mentioned here: https://developer.arm.com/documentation/sden892601/latest/ Change-Id: I13926ceeb7740fa4c05cc5b43170e7ce49598f70 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
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