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92e870843e
Cortex A78 AE erratum 2376748 is a Cat B erratum that applies to revisions <= r0p1. It is still open. The erratum states, "A PE executing a PLDW or PRFM PST instruction that lies on a mispredicted branch path might cause a second PE executing a store exclusive to the same cache line address to fail continuously." The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN is available at https://developer.arm.com/documentation/SDEN-1707912 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d
271 lines
7 KiB
ArmAsm
271 lines
7 KiB
ArmAsm
/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78_ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 1941500.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_1941500_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_1941500
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cbz x0, 1f
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/* Set bit 8 in ECTLR_EL1 */
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mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
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bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
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msr CORTEX_A78_AE_CPUECTLR_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_1941500_wa
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func check_errata_1941500
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_1941500
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 1951502.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_1951502_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_1951502
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cbz x0, 1f
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msr S3_6_c15_c8_0, xzr
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ldr x0, =0x10E3900002
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #1
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #2
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_1951502_wa
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func check_errata_1951502
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_1951502
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 2376748.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_2376748_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_2376748
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cbz x0, 1f
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/* -------------------------------------------------------
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* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
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* behave like PLD/PRFM LD and not cause invalidations to
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* other PE caches. There might be a small performance
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* degradation to this workaround for certain workloads
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* that share data.
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_A78_AE_ACTLR2_EL1
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orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
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msr CORTEX_A78_AE_ACTLR2_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_2376748_wa
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func check_errata_2376748
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_2376748
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78-AE
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* -------------------------------------------------
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*/
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func cortex_a78_ae_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A78_AE_1941500
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mov x0, x18
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bl errata_a78_ae_1941500_wa
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#endif
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#if ERRATA_A78_AE_1951502
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mov x0, x18
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bl errata_a78_ae_1951502_wa
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#endif
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#if ERRATA_A78_AE_2376748
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mov x0, x18
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bl errata_a78_ae_2376748_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A78AE generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a78_ae
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret x19
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endfunc cortex_a78_ae_reset_func
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/* -------------------------------------------------------
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* HW will do the cache maintenance while powering down
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* -------------------------------------------------------
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*/
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func cortex_a78_ae_core_pwr_dwn
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/* -------------------------------------------------------
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* Enable CPU power down bit in power control register
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a78_ae_core_pwr_dwn
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/*
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* Errata printing function for cortex_a78_ae. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_a78_ae_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
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report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
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report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a78_ae_errata_report
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#endif
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/* -------------------------------------------------------
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* This function provides cortex_a78_ae specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* -------------------------------------------------------
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*/
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.section .rodata.cortex_a78_ae_regs, "aS"
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cortex_a78_ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78_ae_cpu_reg_dump
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adr x6, cortex_a78_ae_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_a78_ae_cpu_reg_dump
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declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
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cortex_a78_ae_reset_func, \
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cortex_a78_ae_core_pwr_dwn
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