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fix(errata): workaround for Cortex A78 AE erratum 2376748
Cortex A78 AE erratum 2376748 is a Cat B erratum that applies to revisions <= r0p1. It is still open. The erratum states, "A PE executing a PLDW or PRFM PST instruction that lies on a mispredicted branch path might cause a second PE executing a store exclusive to the same cache line address to fail continuously." The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN is available at https://developer.arm.com/documentation/SDEN-1707912 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d
This commit is contained in:
Varun Wadekar
parent
e638c228b8
commit
92e870843e
5 changed files with 71 additions and 9 deletions
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@ -298,13 +298,17 @@ For Cortex-A78, the following errata build flags are defined :
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For Cortex-A78 AE, the following errata build flags are defined :
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- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78
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AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
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still open.
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- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
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Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
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This erratum is still open.
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- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78
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AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
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still open.
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- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
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Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
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erratum is still open.
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- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
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Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
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erratum is still open.
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For Neoverse N1, the following errata build flags are defined :
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@ -35,6 +35,7 @@
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#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)
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#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -21,4 +21,10 @@
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#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
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#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1
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#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0
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#endif /* CORTEX_A78_AE_H */
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -104,6 +104,43 @@ func check_errata_1951502
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b cpu_rev_var_range
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endfunc check_errata_1951502
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 2376748.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_2376748_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_2376748
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cbz x0, 1f
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/* -------------------------------------------------------
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* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
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* behave like PLD/PRFM LD and not cause invalidations to
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* other PE caches. There might be a small performance
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* degradation to this workaround for certain workloads
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* that share data.
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_A78_AE_ACTLR2_EL1
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orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
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msr CORTEX_A78_AE_ACTLR2_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_2376748_wa
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func check_errata_2376748
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_2376748
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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@ -132,6 +169,11 @@ func cortex_a78_ae_reset_func
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bl errata_a78_ae_1951502_wa
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#endif
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#if ERRATA_A78_AE_2376748
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mov x0, x18
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bl errata_a78_ae_2376748_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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@ -197,6 +239,7 @@ func cortex_a78_ae_errata_report
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*/
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report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
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report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
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report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
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ldp x8, x30, [sp], #16
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@ -1,6 +1,6 @@
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#
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# Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
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# Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -341,6 +341,10 @@ ERRATA_A78_AE_1941500 ?=0
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# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
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ERRATA_A78_AE_1951502 ?=0
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# Flag to apply erratum 2376748 workaround during reset. This erratum applies
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# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
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ERRATA_A78_AE_2376748 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=0
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@ -838,6 +842,10 @@ $(eval $(call add_define,ERRATA_A78_AE_1941500))
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$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
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$(eval $(call add_define,ERRATA_A78_AE_1951502))
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# Process ERRATA_A78_AE_2376748 flag
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$(eval $(call assert_boolean,ERRATA_A78_AE_2376748))
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$(eval $(call add_define,ERRATA_A78_AE_2376748))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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