Varun Wadekar 92e870843e fix(errata): workaround for Cortex A78 AE erratum 2376748 ... Cortex A78 AE erratum 2376748 is a Cat B erratum that applies to revisions <= r0p1. It is still open. The erratum states, "A PE executing a PLDW or PRFM PST instruction that lies on a mispredicted branch path might cause a second PE executing a store exclusive to the same cache line address to fail continuously." The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN is available at https://developer.arm.com/documentation/SDEN-1707912 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d		2022-03-24 10:53:17 +00:00
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aarch32	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
aarch64	fix(errata): workaround for Cortex A78 AE erratum 2376748	2022-03-24 10:53:17 +00:00
errata_report.h	Workaround for Cortex A78 erratum 1951500	2021-01-13 13:54:18 -06:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2022_23960.h	fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57	2022-03-18 01:01:34 +02:00