Jayanth Dodderi Chidanand 7623e085cb feat(cm): test integrity of el1_ctx registers ... * This patch adds support to tsp (BL32) Image, to exercise EL1_context registers at S-EL1. * Adds a SMC function ID "MODIFY_EL1_CTX" to handle EL1_CTX registers at S-EL1 and overwrite them. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: Id4f2b3b748f7bc9e6c9d72a2f03d50aefbfb61cb		2024-11-08 11:05:13 +00:00
..
arm_arch_svc	chore: simplify the macro names in ENABLE_FEAT mechanism	2024-05-02 08:53:01 -05:00
el3	refactor(smccc): move pmf to vendor el3 calls	2024-05-06 09:42:11 -05:00
oem/chromeos	feat(cros_widevine): add ChromeOS widevine SMC handler	2024-02-02 16:41:21 +08:00
spd	feat(cm): test integrity of el1_ctx registers	2024-11-08 11:05:13 +00:00
std_svc	feat(rmmd): el3 token sign during attestation	2024-10-15 08:20:28 -07:00