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https://github.com/ARM-software/arm-trusted-firmware.git
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8cd37d7ba1
BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
28 lines
693 B
C
28 lines
693 B
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SQ_COMMON_H__
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#define __SQ_COMMON_H__
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#include <sys/types.h>
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#include <xlat_tables_v2.h>
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void plat_sq_interconnect_init(void);
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void plat_sq_interconnect_enter_coherency(void);
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void plat_sq_interconnect_exit_coherency(void);
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unsigned int sq_calc_core_pos(u_register_t mpidr);
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void sq_gic_driver_init(void);
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void sq_gic_init(void);
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void sq_gic_cpuif_enable(void);
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void sq_gic_cpuif_disable(void);
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void sq_gic_pcpu_init(void);
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void sq_mmap_setup(uintptr_t total_base, size_t total_size,
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const struct mmap_region *mmap);
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#endif /* __SQ_COMMON_H__ */
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