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https://github.com/ARM-software/arm-trusted-firmware.git
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8b81a39e28
S32G274ARDB2 is a development board to showcase the capabilities of the S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs of DDR, accelerators for automotive networking and many other peripherals. The added support is minimal and only includes the BL2 stage, with no MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies BL31 and BL33 from FIP to their designated addresses. Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842 Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> Signed-off-by: Dan Nica <dan.nica@nxp.com> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
129 lines
2.7 KiB
ArmAsm
129 lines
2.7 KiB
ArmAsm
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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#define S32G_NCORE_CAIU0_BASE_ADDR UL(0x50400000)
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#define S32G_NCORE_CAIUTC_OFF U(0x0)
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#define S32G_NCORE_CAIUTC_ISOLEN_SHIFT U(1)
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.globl plat_crash_console_flush
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_is_my_cpu_primary
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.globl plat_reset_handler
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.globl plat_secondary_cold_boot_setup
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.globl platform_mem_init
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.globl s32g2_core_pos_by_mpidr
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/* int plat_crash_console_init(void); */
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func plat_crash_console_init
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mov_imm x0, UART_BASE
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mov_imm x1, UART_CLOCK_HZ
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mov_imm x2, UART_BAUDRATE
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b console_linflex_core_init
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endfunc plat_crash_console_init
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/* int plat_crash_console_putc(int); */
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func plat_crash_console_putc
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mov_imm x1, UART_BASE
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b console_linflex_core_putc
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ret
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endfunc plat_crash_console_putc
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/* void plat_crash_console_flush(void); */
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func plat_crash_console_flush
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ret
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endfunc plat_crash_console_flush
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/**
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* unsigned int s32g2_core_pos_by_mpidr(u_register_t mpidr);
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*
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* In: x0 - MPIDR_EL1
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* Out: x0
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* Clobber list: x0, x1
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*/
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func s32g2_core_pos_by_mpidr
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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lsr x0, x0, #MPIDR_AFF1_SHIFT
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add x0, x1, x0, lsl #PLATFORM_MPIDR_CPU_MASK_BITS
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ret
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endfunc s32g2_core_pos_by_mpidr
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/**
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* unsigned int plat_my_core_pos(void);
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*
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* Out: x0
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* Clobber list: x0, x1, x8
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*/
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func plat_my_core_pos
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mov x8, x30
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mrs x0, mpidr_el1
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bl s32g2_core_pos_by_mpidr
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mov x30, x8
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ret
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endfunc plat_my_core_pos
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/**
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* unsigned int plat_is_my_cpu_primary(void);
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*
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* Clobber list: x0, x1, x7, x8
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*/
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func plat_is_my_cpu_primary
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mov x7, x30
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bl plat_my_core_pos
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cmp x0, #PLATFORM_PRIMARY_CPU
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cset x0, eq
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mov x30, x7
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ret
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endfunc plat_is_my_cpu_primary
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/**
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* void plat_secondary_cold_boot_setup (void);
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*/
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func plat_secondary_cold_boot_setup
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ret
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endfunc plat_secondary_cold_boot_setup
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/**
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* void plat_reset_handler(void);
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*
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* Set the CAIUTC[IsolEn] bit for the primary A53 cluster.
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* This is so cache invalidate operations from the early TF-A boot code
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* won't cause Ncore to crash.
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*
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* Clobber list: x0, x1, x2
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*/
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func plat_reset_handler
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mov x0, #S32G_NCORE_CAIU0_BASE_ADDR
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ldr w1, [x0, #S32G_NCORE_CAIUTC_OFF]
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movz w2, #1
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lsl w2, w2, #S32G_NCORE_CAIUTC_ISOLEN_SHIFT
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orr w1, w1, w2
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str w1, [x0, #S32G_NCORE_CAIUTC_OFF]
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ret
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endfunc plat_reset_handler
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/* void platform_mem_init(void); */
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func platform_mem_init
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mov x10, x30
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mov x0, #BL31_BASE
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mov x1, #(BL31_LIMIT & 0xFFFFU)
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movk x1, #(BL31_LIMIT >> 16), lsl #16
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sub x1, x1, x0
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bl zeromem
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mov x0, #BL33_BASE
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mov x1, #(BL33_LIMIT & 0xFFFFU)
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movk x1, #(BL33_LIMIT >> 16), lsl #16
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sub x1, x1, x0
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bl zeromem
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mov x30, x10
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ret
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endfunc platform_mem_init
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