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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpuamu.h>
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#include <lib/el3_runtime/pubsub_events.h>
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#include <plat/common/platform.h>
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#define CPUAMU_NR_COUNTERS 5U
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struct cpuamu_ctx {
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uint64_t cnts[CPUAMU_NR_COUNTERS];
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unsigned int mask;
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};
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static struct cpuamu_ctx cpuamu_ctxs[PLATFORM_CORE_COUNT];
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int midr_match(unsigned int cpu_midr)
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{
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unsigned int midr, midr_mask;
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midr = (unsigned int)read_midr();
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midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
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(MIDR_PN_MASK << MIDR_PN_SHIFT);
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return ((midr & midr_mask) == (cpu_midr & midr_mask));
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}
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void cpuamu_context_save(unsigned int nr_counters)
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{
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struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
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unsigned int i;
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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/* Save counter configuration */
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ctx->mask = cpuamu_read_cpuamcntenset_el0();
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/* Disable counters */
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cpuamu_write_cpuamcntenclr_el0(ctx->mask);
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isb();
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/* Save counters */
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for (i = 0; i < nr_counters; i++)
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ctx->cnts[i] = cpuamu_cnt_read(i);
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}
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void cpuamu_context_restore(unsigned int nr_counters)
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{
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struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
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unsigned int i;
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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/*
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* Disable counters. They were enabled early in the
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* CPU reset function.
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*/
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cpuamu_write_cpuamcntenclr_el0(ctx->mask);
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isb();
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/* Restore counters */
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for (i = 0; i < nr_counters; i++)
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cpuamu_cnt_write(i, ctx->cnts[i]);
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isb();
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/* Restore counter configuration */
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cpuamu_write_cpuamcntenset_el0(ctx->mask);
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}
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