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https://github.com/ARM-software/arm-trusted-firmware.git
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076b5f02e2
This patch fixes this issue: https://github.com/ARM-software/tf-issues/issues/660 The introduced changes are the following: 1) Some cores implement cache coherency maintenance operation on the hardware level. For those cores, such as - but not only - the DynamIQ cores, it is mandatory that TF-A is compiled with the HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is unpredictable. To prevent this, compile time checks have been added and compilation errors are generated, if needed. 2) To enable this change for FVP, a logical separation has been done for the core libraries. A system cannot contain cores of both groups, i.e. cores that manage coherency on hardware and cores that don't do it. As such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the libraries only of the relevant cores. 3) The neoverse_e1.S file has been added to the FVP sources. Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
229 lines
5.3 KiB
ArmAsm
229 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cortex_a75.h>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A75 Errata #764081.
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* This applies only to revision r0p0 of Cortex A75.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a75_764081_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_764081
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cbz x0, 1f
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mrs x1, sctlr_el3
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orr x1, x1 ,#SCTLR_IESB_BIT
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msr sctlr_el3, x1
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isb
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1:
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ret x17
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endfunc errata_a75_764081_wa
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func check_errata_764081
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_764081
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/* --------------------------------------------------
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* Errata Workaround for Cortex A75 Errata #790748.
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* This applies only to revision r0p0 of Cortex A75.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a75_790748_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_790748
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cbz x0, 1f
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mrs x1, CORTEX_A75_CPUACTLR_EL1
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orr x1, x1 ,#(1 << 13)
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msr CORTEX_A75_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a75_790748_wa
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func check_errata_790748
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_790748
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A75.
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* -------------------------------------------------
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*/
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func cortex_a75_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A75_764081
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mov x0, x18
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bl errata_a75_764081_wa
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#endif
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#if ERRATA_A75_790748
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mov x0, x18
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bl errata_a75_790748_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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cpu_check_csv2 x0, 1f
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adr x0, wa_cve_2017_5715_bpiall_vbar
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msr vbar_el3, x0
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isb
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1:
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#endif
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#if WORKAROUND_CVE_2018_3639
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mrs x0, CORTEX_A75_CPUACTLR_EL1
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orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
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msr CORTEX_A75_CPUACTLR_EL1, x0
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isb
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#endif
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#if ERRATA_DSU_798953
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bl errata_dsu_798953_wa
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#endif
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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isb
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/* Enable group0 counters */
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mov x0, #CORTEX_A75_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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/* Enable group1 counters */
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mov x0, #CORTEX_A75_AMU_GROUP1_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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#endif
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ret x19
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endfunc cortex_a75_reset_func
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func check_errata_cve_2017_5715
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cpu_check_csv2 x0, 1f
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#if WORKAROUND_CVE_2017_5715
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_errata_cve_2017_5715
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func check_errata_cve_2018_3639
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#if WORKAROUND_CVE_2018_3639
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2018_3639
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a75_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
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msr CORTEX_A75_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a75_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A75. Must follow AAPCS.
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*/
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func cortex_a75_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A75_764081, cortex_a75, 764081
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report_errata ERRATA_A75_790748, cortex_a75, 790748
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report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
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report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
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report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953
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report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a75_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a75 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a75_regs, "aS"
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cortex_a75_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a75_cpu_reg_dump
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adr x6, cortex_a75_regs
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mrs x8, CORTEX_A75_CPUECTLR_EL1
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ret
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endfunc cortex_a75_cpu_reg_dump
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declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
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cortex_a75_reset_func, \
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check_errata_cve_2017_5715, \
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CPU_NO_EXTRA2_FUNC, \
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cortex_a75_core_pwr_dwn
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