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Add compile-time errors for HW_ASSISTED_COHERENCY flag

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This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.

2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.

3) The neoverse_e1.S file has been added to the FVP sources.

Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
This commit is contained in:
John Tsichritzis 2019-03-19 17:20:52 +00:00
parent 9a25f98261
commit 076b5f02e2
10 changed files with 72 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
docs/user-guide.rst
View file

@ -530,13 +530,21 @@ Common build options
- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
software operations are required for CPUs to enter and exit coherency.
However, there exists newer systems where CPUs' entry to and exit from
coherency is managed in hardware. Such systems require software to only
initiate the operations, and the rest is managed in hardware, minimizing
active software management. In such systems, this boolean option enables
TF-A to carry out build and run-time optimizations during boot and power
management operations. This option defaults to 0 and if it is enabled,
then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
However, newer systems exist where CPUs' entry to and exit from coherency
is managed in hardware. Such systems require software to only initiate these
operations, and the rest is managed in hardware, minimizing active software
management. In such systems, this boolean option enables TF-A to carry out
build and run-time optimizations during boot and power management operations.
This option defaults to 0 and if it is enabled, then it implies
``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
If this flag is disabled while the platform which TF-A is compiled for
includes cores that manage coherency in hardware, then a compilation error is
generated. This is based on the fact that a system cannot have, at the same
time, cores that manage coherency in hardware and cores that don't. In other
words, a platform cannot have, at the same time, cores that require
``HW_ASSISTED_COHERENCY=1`` and cores that require
``HW_ASSISTED_COHERENCY=0``.
Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
translation library (xlat tables v2) must be used; version 1 of translation

5
lib/cpus/aarch64/cortex_a55.S
View file

@ -11,6 +11,11 @@
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* --------------------------------------------------
* Errata Workaround for Cortex A55 Errata #768277.
* This applies only to revision r0p0 of Cortex A55.

5
lib/cpus/aarch64/cortex_a75.S
View file

@ -10,6 +10,11 @@
#include <cpuamu.h>
#include <cpu_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* --------------------------------------------------
* Errata Workaround for Cortex A75 Errata #764081.
* This applies only to revision r0p0 of Cortex A75.

5
lib/cpus/aarch64/cortex_a76.S
View file

@ -13,6 +13,11 @@
#include <plat_macros.S>
#include <services/arm_arch_svc.h>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
#define ESR_EL3_A64_SMC0 0x5e000000
#define ESR_EL3_A32_SMC0 0x4e000000

5
lib/cpus/aarch64/cortex_a76ae.S
View file

@ -8,6 +8,11 @@
#include <cortex_a76ae.h>
#include <cpu_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------

7
lib/cpus/aarch64/cortex_deimos.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -11,6 +11,11 @@
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------

5
lib/cpus/aarch64/neoverse_e1.S
View file

@ -11,6 +11,11 @@
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
func neoverse_e1_cpu_pwr_dwn
mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT

5
lib/cpus/aarch64/neoverse_n1.S
View file

@ -10,6 +10,11 @@
#include <cpuamu.h>
#include <cpu_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata
* This applies to revision r0p0 and r1p0 of Neoverse N1.

5
lib/cpus/aarch64/neoverse_zeus.S
View file

@ -11,6 +11,11 @@
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------

22
plat/arm/board/fvp/platform.mk
View file

@ -95,18 +95,25 @@ PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
ifeq (${ARCH}, aarch64)
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
# select a different set of CPU files, depending on whether we compile with
# hardware assisted coherency configurations or not
ifeq (${HW_ASSISTED_COHERENCY}, 0)
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a73.S \
lib/cpus/aarch64/cortex_a73.S
else
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a75.S \
lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/cortex_deimos.S \
lib/cpus/aarch64/neoverse_zeus.S
endif
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
@ -217,10 +224,13 @@ ENABLE_PIE := 1
endif
ifeq (${ENABLE_AMU},1)
BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
lib/cpus/aarch64/neoverse_n1_pubsub.c \
lib/cpus/aarch64/cpuamu.c \
BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
lib/cpus/aarch64/cpuamu_helpers.S
ifeq (${HW_ASSISTED_COHERENCY}, 1)
BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
lib/cpus/aarch64/neoverse_n1_pubsub.c
endif
endif
ifeq (${RAS_EXTENSION},1)