Rohit Mathew b77f55d6c7 feat(cpu): add support for Poseidon V CPU ... Enable support for Poseidon V CPUs. Poseidon V CPUs are distinguished by a 3MB L2 cache, differing from Poseidon VN(AE) CPUs with a 2MB L2 cache. This enhancement ensures compatibility with RD-Fremont and similar platforms utilizing Poseidon V CPUs. CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: Icdcc5f57c62855b2ec54c58a401d3bf09f292189		2024-01-04 19:06:38 +00:00
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aarch32	refactor(cpus): add Cortex-A57 errata framework information	2023-08-24 14:27:42 -05:00
aarch64	feat(cpu): add support for Poseidon V CPU	2024-01-04 19:06:38 +00:00
cpu-ops.mk	Merge "fix(cpus): workaround for Cortex X3 erratum 2743088" into integration	2023-12-21 18:07:00 +01:00
errata_report.c	fix(cpus): reduce generic_errata_report()'s size	2023-06-15 10:14:59 +01:00