arm-trusted-firmware/plat
Andre Przywara 7db710f0cb refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
At the moment we only support FEAT_CSV2_2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting
is_armv8_0_feat_csv2_2_present() into an ID register reading function
and a second function to report the support status. That function
considers both build time settings and runtime information (if needed),
and is used before we access the SCXTNUM_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_csv2_2_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-03-22 13:33:22 +00:00
..
allwinner refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS 2023-03-20 13:37:36 +00:00
amlogic
arm refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED 2023-03-22 13:33:22 +00:00
brcm refactor(libc): clean up dependencies in libc 2022-09-22 13:23:49 +02:00
common Merge changes from topic "panic_cleanup" into integration 2023-02-23 23:38:26 +01:00
hisilicon refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
imx refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
intel/soc refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
marvell build: always prefix section names with . 2023-02-20 18:29:33 +00:00
mediatek Merge changes I924ea85d,I22e128c4,I7a5cfaac into integration 2023-03-21 10:46:41 +01:00
nvidia/tegra Merge "fix(tegra): append major revision to the chip_id value" into integration 2023-03-13 17:52:15 +01:00
nxp refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
qemu Merge changes from topics "qemu", "qemu_sbsa" into integration 2023-03-20 22:21:24 +01:00
qti refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS 2023-03-20 13:37:36 +00:00
renesas refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
rockchip style: remove useless trailing semicolon and line continuations 2023-03-09 14:59:08 +01:00
rpi fix(rpi3): tighten platform pwr_domain_pwr_down_wfi behaviour 2022-10-27 13:46:02 +01:00
socionext refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
st refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
ti/k3 fix(ti): do not take system power reference in bl31_platform_setup() 2023-03-07 09:22:32 -06:00
xilinx fix(versal_net): fix irq for IPI0 2023-03-14 12:25:03 -07:00