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7b41acaf72
EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1 register for gelas cpu enables external Last-level cache in the system, External LLC is present on TC4 systems in MCN but it is not enabled in CPU registers so enable it. On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC so take care of that as well. Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3 Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
106 lines
2.7 KiB
ArmAsm
106 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <cpu_macros.S>
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#include <cortex_gelas.h>
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#define TC_HANDLER(rev) plat_reset_handler_tc##rev
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#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
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.globl plat_arm_calc_core_pos
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.globl plat_reset_handler
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/* ---------------------------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Function to calculate the core position on TC.
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*
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* (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
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* (CPUId * PLAT_MAX_PE_PER_CPU) +
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* ThreadId
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*
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* which can be simplified as:
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*
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* ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
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* + ThreadId
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* ---------------------------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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/*
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* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
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* look as if in a multi-threaded implementation.
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*/
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tst x0, #MPIDR_MT_MASK
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lsl x3, x0, #MPIDR_AFFINITY_BITS
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csel x3, x3, x0, eq
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/* Extract individual affinity fields from MPIDR */
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ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
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madd x1, x2, x4, x1
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mov x5, #PLAT_MAX_PE_PER_CPU
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madd x0, x1, x5, x0
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ret
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endfunc plat_arm_calc_core_pos
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func mark_extllc_presence
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#ifdef MCN_CONFIG_ADDR
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mov_imm x0, (MCN_CONFIG_ADDR(0))
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ldr w1, [x0]
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ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
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jump_if_cpu_midr CORTEX_GELAS_MIDR, GELAS
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sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, CPUECTLR_EL1_EXTLLC_BIT, 1
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ret
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GELAS:
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sysreg_bitfield_insert_from_gpr CORTEX_GELAS_IMP_CPUECTLR_EL1, x1, CPUECTLR2_EL1_EXTLLC_BIT, 1
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#endif
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ret
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endfunc mark_extllc_presence
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func enable_dsu_pmu_el1_access
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sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN
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sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN
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ret
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endfunc enable_dsu_pmu_el1_access
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func TC_HANDLER(2)
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ret
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endfunc TC_HANDLER(2)
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func TC_HANDLER(3)
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mov x9, lr
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bl mark_extllc_presence
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bl enable_dsu_pmu_el1_access
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mov lr, x9
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ret
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endfunc TC_HANDLER(3)
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func TC_HANDLER(4)
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mov x9, lr
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bl mark_extllc_presence
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bl enable_dsu_pmu_el1_access
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mov lr, x9
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ret
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endfunc TC_HANDLER(4)
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/* -----------------------------------------------------
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* void plat_reset_handler(void);
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* -----------------------------------------------------
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*/
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func plat_reset_handler
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mov x8, lr
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bl PLAT_RESET_HANDLER(TARGET_PLATFORM)
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mov lr, x8
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ret
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endfunc plat_reset_handler
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