Jagdish Gediya 7b41acaf72 fix(tc): enable Last-level cache (LLC) for tc4 ... EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1 register for gelas cpu enables external Last-level cache in the system, External LLC is present on TC4 systems in MCN but it is not enabled in CPU registers so enable it. On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC so take care of that as well. Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3 Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>		2025-01-23 16:03:48 +00:00
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a5ds	refactor(arm): replace hard-coded HW_CONFIG DT size	2024-04-12 06:28:33 +00:00
arm_fpga	perf(build): be clever about uppercasing	2024-11-08 12:27:46 +00:00
automotive_rd/platform/rd1ae	feat(rd1ae): add support for OP-TEE SPMC	2024-11-14 13:56:39 +00:00
common	refactor(arm): rename ARM_ROTPK_HEADER_LEN	2024-12-30 12:32:34 +01:00
corstone700	build(bl32): added check for AARCH32_SP	2023-08-24 14:22:34 -05:00
corstone1000	fix(corstone-1000): fix Makefile error reporting	2024-08-27 10:39:41 +01:00
fvp	Merge changes from topic "hm/heap-info" into integration	2024-12-18 17:56:44 +01:00
fvp_r	fix(arm): add extra hash config to validate ROTPK	2024-09-09 11:22:28 +01:00
fvp_ve	feat(fvp): add flash areas for secure partition	2024-07-29 09:55:43 +01:00
juno	refactor(arm): rename ARM_ROTPK_HEADER_LEN	2024-12-30 12:32:34 +01:00
morello	build: remove MAKE_BUILD_STRINGS function	2024-04-29 12:47:01 +00:00
n1sdp	refactor(arm): remove unused SP_MIN UART macros	2024-04-02 13:36:31 +01:00
neoverse_rd	fix(neoverse-rd): initialize timer before use in smmuv3_poll	2024-12-23 13:06:26 +05:30
tc	fix(tc): enable Last-level cache (LLC) for tc4	2025-01-23 16:03:48 +00:00