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7954412694
Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions r0p0 and r1p0, and is fixed in r1p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset. SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I5935b4bcd1e6712477c0d6eab2acc96d7964a35d
32 lines
1.2 KiB
C
32 lines
1.2 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X3_H
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#define CORTEX_X3_H
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#define CORTEX_X3_MIDR U(0x410FD4E0)
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/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
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#endif /* CORTEX_X3_H */
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