Igor Podgainõi 58fadd62be fix: add support for 128-bit sysregs to EL3 crash handler ... The following changes have been made: * Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm * Add registers TTBR0_EL2 and VTTBR_EL2 to EL3 crash handler output * Use MRRS instead of MRS for registers TTBR0_EL1, TTBR0_EL2, TTBR1_EL1, VTTBR_EL2 and PAR_EL1 Change-Id: I0e20b2c35251f3afba2df794c1f8bc0c46c197ff Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>		2025-02-05 21:19:15 +01:00
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amu	refactor(cm): move EL3 registers to global context	2023-10-31 11:18:42 +00:00
brbe	refactor(cm): change owning security state when a feature is disabled	2025-01-06 07:38:23 +00:00
debug	feat(debugv8p9): add support for FEAT_Debugv8p9	2024-07-18 13:49:43 -05:00
fgt	feat(fgt2): add support for FEAT_FGT2	2024-07-18 13:49:43 -05:00
fpmr	feat(fpmr): disable FPMR trap	2024-12-12 10:03:23 -06:00
mpam	refactor(cm): move MPAM3_EL3 reg to per world context	2023-12-21 12:37:21 +00:00
pauth	chore(pauth): remove redundant pauth_disable_el3() call	2023-04-28 08:09:14 +01:00
pmuv3	feat(pmuv3): setup per world MDCR_EL3	2025-01-24 10:09:08 +00:00
ras	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
sme	refactor(cpufeat): add macro to simplify is_feat_xx_present	2024-05-02 12:16:16 -05:00
spe	fix(cm): change back owning security state when a feature is disabled	2025-01-14 09:06:37 +00:00
sve	refactor(cm): move EL3 registers to global context	2023-10-31 11:18:42 +00:00
sys_reg_trace	refactor(cm): move EL3 registers to global context	2023-10-31 11:18:42 +00:00
sysreg128	fix: add support for 128-bit sysregs to EL3 crash handler	2025-02-05 21:19:15 +01:00
tcr	feat(cm): handle asymmetry for FEAT_TCR2	2024-09-05 16:28:23 +01:00
trbe	fix(cm): change back owning security state when a feature is disabled	2025-01-14 09:06:37 +00:00
trf	feat(cm): context switch MDCR_EL3 register	2024-06-25 13:50:32 +01:00