Amit Nagal 46a08aab4c feat(versal-net): ddr address reservation in dtb at runtime ... When the TF-A is placed in DDR memory range, the DDR memory range needs to be explicitly reserved in the default device tree. A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced. The TF-A will reserve the DDR memory only when a valid DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build. Now the user has options, either manually reserve the desired DDR address range for TF-A in device tree or let TF-A access and modify the device tree, to reserve the DDR address range, in runtime using the build parameter. Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a Signed-off-by: Amit Nagal <amit.nagal@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>		2023-07-13 09:20:43 +05:30
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common	feat(versal): ddr address reservation in dtb at runtime	2023-07-13 09:20:32 +05:30
versal	feat(versal): ddr address reservation in dtb at runtime	2023-07-13 09:20:32 +05:30
versal_net	feat(versal-net): ddr address reservation in dtb at runtime	2023-07-13 09:20:43 +05:30
zynqmp	Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration	2023-07-04 19:12:40 +02:00