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14a6fed5ac
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to revision r0p0. It is fixed in r1p0. The workaround is done through the instruction patching mechanism, which is performed by a write sequence of IMPLEMENTATION DEFINED registers. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401781/latest/ Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168
44 lines
1.8 KiB
C
44 lines
1.8 KiB
C
/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_V1_H
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#define NEOVERSE_V1_H
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#define NEOVERSE_V1_MIDR U(0x410FD400)
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/* Neoverse V1 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V1_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
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#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
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#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
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#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
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#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
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#define CPUECTLR_EL1_PF_MODE_LSB U(6)
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#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
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#endif /* NEOVERSE_V1_H */
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