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24dba2b39f
The platform port documents are not very standardised right now and they don't integrate properly into the document tree so: 1) Make sure each port has a proper name and title (incl. owner) 2) Correct use of headings, subheadings, etc in each port 3) Resolve any naming conflicts between documents Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
67 lines
2.1 KiB
ReStructuredText
67 lines
2.1 KiB
ReStructuredText
Xilinx Zynq UltraScale+ MPSoC
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=============================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq
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UltraScale + MPSoC.
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The platform only uses the runtime part of TF-A as ZynqMP already has a
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BootROM (BL1) and FSBL (BL2).
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BL31 is TF-A.
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BL32 is an optional Secure Payload.
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BL33 is the non-secure world software (U-Boot, Linux etc).
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To build:
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.. code:: bash
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31
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To build bl32 TSP you have to rebuild bl31 too:
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.. code:: bash
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
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ZynqMP platform specific build options
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--------------------------------------
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- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
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- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
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- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
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- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary.
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- ``ZYNQMP_CONSOLE``: Select the console driver. Options:
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- ``cadence``, ``cadence0``: Cadence UART 0
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- ``cadence1`` : Cadence UART 1
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FSBL->TF-A Parameter Passing
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----------------------------
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The FSBL populates a data structure with image information for TF-A. TF-A uses
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that data to hand off to the loaded images. The address of the handoff data
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structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The
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register is free to be used by other software once TF-A has brought up
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further firmware images.
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Power Domain Tree
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-----------------
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The following power domain tree represents the power domain model used by TF-A
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for ZynqMP:
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::
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+-+
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|0|
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+-+
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+-------+---+---+-------+
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v v v v
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+-+ +-+ +-+ +-+
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|0| |1| |2| |3|
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+-+ +-+ +-+ +-+
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The 4 leaf power domains represent the individual A53 cores, while resources
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common to the cluster are grouped in the power domain on the top.
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