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arm-trusted-firmware/lib/cpus/aarch32
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Ambroise Vincent 5f2c690d0e Cortex-A15: Implement workaround for errata 827671 
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html

Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13 14:05:47 +00:00
..
aem_generic.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a5.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a7.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a9.S Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 2018-01-18 10:36:25 +00:00
cortex_a12.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a15.S Cortex-A15: Implement workaround for errata 827671 2019-03-13 14:05:47 +00:00
cortex_a17.S Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 2018-01-18 10:36:25 +00:00
cortex_a32.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a53.S Cortex-A53: Workarounds for 819472, 824069 and 827319 2019-02-28 09:56:58 +00:00
cortex_a57.S Cortex-A57: Implement workaround for erratum 817169 2019-02-28 09:56:58 +00:00
cortex_a72.S Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
cpu_helpers.S Fixup register handling in aarch32 reset_handler 2019-03-08 15:35:30 +00:00