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59902b7c4c
A new platform macro `PLAT_AMU_GROUP1_COUNTERS_MASK` controls which group 1 counters should be enabled. The maximum number of group 1 counters supported by AMUv1 is 16 so the mask can be at most 0xffff. If the platform does not define this mask, no group 1 counters are enabled. A related platform macro `PLAT_AMU_GROUP1_NR_COUNTERS` is used by generic code to allocate an array to save and restore the counters on CPU suspend. Change-Id: I6d135badf4846292de931a43bb563077f42bb47b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
42 lines
940 B
C
42 lines
940 B
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <amu.h>
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#include <arch.h>
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#include <arch_helpers.h>
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void amu_enable(int el2_unused)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
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if ((features & ID_AA64PFR0_AMU_MASK) == 1) {
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uint64_t v;
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if (el2_unused) {
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/*
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* CPTR_EL2.TAM: Set to zero so any accesses to
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* the Activity Monitor registers do not trap to EL2.
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*/
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v = read_cptr_el2();
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v &= ~CPTR_EL2_TAM_BIT;
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write_cptr_el2(v);
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}
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/*
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* CPTR_EL3.TAM: Set to zero so that any accesses to
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* the Activity Monitor registers do not trap to EL3.
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*/
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v = read_cptr_el3();
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v &= ~TAM_BIT;
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write_cptr_el3(v);
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/* Enable group 0 counters */
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write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
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/* Enable group 1 counters */
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write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
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}
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}
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