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57536653e6
If PLATFORM_STACK_SIZE not already defined, use the default value of PLATFORM_STACK_SIZE. This makes the stack size value configurable for different interface like custom packages. Signed-off-by: Amit Nagal <amit.nagal@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com> Change-Id: I87e9fcbfb4c4092378b1ac0ff8fb6d084495d320
177 lines
6.1 KiB
C
177 lines
6.1 KiB
C
/*
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* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/utils_def.h>
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#include "zynqmp_def.h"
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#ifndef PLATFORM_STACK_SIZE
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#define PLATFORM_STACK_SIZE 0x440
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#endif
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#define PLATFORM_CORE_COUNT U(4)
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#define PLAT_NUM_POWER_DOMAINS U(5)
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#define PLAT_MAX_PWR_LVL U(1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#ifndef ZYNQMP_ATF_MEM_BASE
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#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
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# define BL31_BASE U(0xfffea000)
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# define BL31_LIMIT U(0x100000000)
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#else
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# define BL31_BASE U(0x1000)
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# define BL31_LIMIT U(0x7ffff)
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#endif
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#else
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# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
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# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
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# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
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# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1)
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# endif
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#endif
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#ifndef ZYNQMP_BL32_MEM_BASE
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# define BL32_BASE U(0x60000000)
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# define BL32_LIMIT U(0x7fffffff)
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#else
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# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
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# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
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#endif
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/*******************************************************************************
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* BL33 specific defines.
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******************************************************************************/
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#ifndef PRELOADED_BL33_BASE
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# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
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#else
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# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
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#endif
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/*******************************************************************************
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* TSP specific defines.
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******************************************************************************/
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
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/* ID of the secure physical generic timer interrupt used by the TSP */
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#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
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#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
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#define PLAT_OCM_BASE U(0xFFFC0000)
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#define PLAT_OCM_LIMIT U(0xFFFFFFFF)
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#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT))
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#ifndef MAX_MMAP_REGIONS
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#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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#define MAX_MMAP_REGIONS 8
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#else
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#define MAX_MMAP_REGIONS 7
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#endif
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#endif
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#ifndef MAX_XLAT_TABLES
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#if !IS_TFA_IN_OCM(BL31_BASE)
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#define MAX_XLAT_TABLES 8
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#else
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#define MAX_XLAT_TABLES 5
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#endif
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#endif
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define ZYNQMP_SDEI_SGI_PRIVATE U(8)
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/* Platform macros to support exception handling framework */
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#define PLAT_PRI_BITS U(3)
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#define PLAT_SDEI_CRITICAL_PRI 0x10
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#define PLAT_SDEI_NORMAL_PRI 0x20
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#if !ZYNQMP_WDT_RESTART
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#else
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#endif
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#define PLAT_ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
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GIC_INTR_CFG_EDGE)
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#endif /* PLATFORM_DEF_H */
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