Ghennadi Procopciuc c23dde6c19 feat(nxp-clk): restore pll output dividers rate ... Reconfiguration of the PLL may be requested while some output dividers are already enabled. To prevent setting a different frequency for these enabled dividers, the driver will attempt to adjust the division factor to achieve the initially requested rate. Change-Id: I7800c05b2f21bbdeda243db865942b647983687d Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>		2025-01-23 13:13:24 +02:00
..
include	feat(nxp-clk): add get_rate for s32cc_pll	2025-01-23 13:13:24 +02:00
mc_me.c	feat(nxp-clk): add MC_ME utilities	2024-09-30 14:16:00 +03:00
mc_rgm.c	feat(nxp-clk): add partition reset utilities	2024-09-30 14:16:00 +03:00
s32cc_clk.mk	feat(nxp-clk): add MC_ME utilities	2024-09-30 14:16:00 +03:00
s32cc_clk_drv.c	feat(nxp-clk): restore pll output dividers rate	2025-01-23 13:13:24 +02:00
s32cc_clk_modules.c	feat(nxp-clk): add a basic get_rate implementation	2025-01-23 13:13:22 +02:00
s32cc_clk_utils.c	feat(nxp-clk): add get_parent callback	2024-09-20 11:33:30 +03:00
s32cc_early_clks.c	feat(s32g274a): split early clock initialization	2025-01-14 13:02:51 +02:00