Thomas Abraham 54b86d47eb fix(cpus): fix incorrect AMU trap settings for N2 CPU ... The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset handling sequence of the Neoverse N2 CPU. As these bits are set, any access of AMU registers from EL0/EL1 and EL2 respectively are incorrectly trapped to a higher EL. Fix this by clearing the TAM bits in both the CPTR_EL2 and CPTR_EL3 registers. Signed-off-by: Thomas Abraham <thomas.abraham@arm.com> Change-Id: I357b16dfc7d7367b8a0c8086faac28f3e2866cd8		2023-12-10 17:01:44 +00:00
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aarch32	refactor(cpus): add Cortex-A57 errata framework information	2023-08-24 14:27:42 -05:00
aarch64	fix(cpus): fix incorrect AMU trap settings for N2 CPU	2023-12-10 17:01:44 +00:00
cpu-ops.mk	Merge "fix(cpus): workaround for Neoverse V2 erratum 2618597" into integration	2023-11-29 23:40:05 +01:00
errata_report.c	fix(cpus): reduce generic_errata_report()'s size	2023-06-15 10:14:59 +01:00