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fix(cpus): fix incorrect AMU trap settings for N2 CPU

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The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset
handling sequence of the Neoverse N2 CPU. As these bits are set, any
access of AMU registers from EL0/EL1 and EL2 respectively are
incorrectly trapped to a higher EL. Fix this by clearing the TAM bits in
both the CPTR_EL2 and CPTR_EL3 registers.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I357b16dfc7d7367b8a0c8086faac28f3e2866cd8
This commit is contained in:
Thomas Abraham 2023-12-10 14:15:44 +00:00
parent c0ae04ad4e
commit 54b86d47eb
1 changed files with 2 additions and 2 deletions
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4
lib/cpus/aarch64/neoverse_n2.S
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@ -252,9 +252,9 @@ cpu_reset_func_start neoverse_n2
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
sysreg_bit_set cptr_el3, TAM_BIT
sysreg_bit_clear cptr_el3, TAM_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
sysreg_bit_set cptr_el2, TAM_BIT
sysreg_bit_clear cptr_el2, TAM_BIT
/* No need to enable the counters as this would be done at el3 exit */
#endif