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81d4094d63
Cortex-A78C erratum 2743232 is a Cat B erratum that applies to revisions r0p1 and r0p2 and is still open. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN Documentation: https://developer.arm.com/documentation/SDEN-2004089/latest Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
55 lines
2.4 KiB
C
55 lines
2.4 KiB
C
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A78C_H
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#define CORTEX_A78C_H
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#define CORTEX_A78C_MIDR U(0x410FD4B1)
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/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A78C_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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* ****************************************************************************/
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#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
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#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6)
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#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7)
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#define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register 3 specific definitions.
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******************************************************************************/
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#define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2
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/*******************************************************************************
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* CPU Implementation Specific Selected Instruction registers
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******************************************************************************/
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#define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define CORTEX_A78C_ACTLR5_EL1 S3_0_C15_C9_0
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#endif /* CORTEX_A78C_H */
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