Benjamin Fair 529b541e8b drivers: ti: uart: Add TI specific 16550 initialization ... On TI platforms the UART is disabled by default and must be explicitly enabled using the MDR1 register. NOTE: The original definition of http://www.ti.com/lit/ds/symlink/pc16550d.pdf has no MDR register, but many TI SoCs implementing 16550 do have a quirky MDR register implemented. So, this should be enabled with TI_16550_MDR_QUIRK NOTE: In such implementation, the CSR register does not exist. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>		2018-06-11 14:26:32 -05:00
..
arm	Merge pull request #1340 from Andre-ARM/sec-irqs-fixes	2018-05-17 14:35:34 +01:00
auth	Dynamic cfg: Enable support on CoT for other configs	2018-05-18 12:26:38 +01:00
cadence/uart	drivers: cadence: cdns: Update CDNS driver to support MULTI_CONSOLE_API	2018-01-19 15:21:12 -08:00
console	Ensure read and write of flags are 32 bit	2018-05-17 16:42:41 +01:00
coreboot/cbmem_console/aarch64	coreboot: Add support for CBMEM console	2018-01-19 15:21:12 -08:00
delay_timer	Fix MISRA rule 8.3 in common code	2018-02-28 17:18:21 +00:00
emmc	emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8	2018-01-17 14:14:29 +08:00
gpio	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
io	Fix MISRA rule 8.4 in common code	2018-02-28 17:18:46 +00:00
partition	Fix order of #includes	2017-07-12 14:45:31 +01:00
synopsys	drivers: fix switch statements to comply with MISRA rules	2018-03-26 12:43:05 +01:00
ti/uart	drivers: ti: uart: Add TI specific 16550 initialization	2018-06-11 14:26:32 -05:00
ufs	drivers: fix switch statements to comply with MISRA rules	2018-03-26 12:43:05 +01:00