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https://github.com/ARM-software/arm-trusted-firmware.git
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4caef42a94
This patch adds new cpu ops function extra4 and a new macro for CVE-2024-7881 [1]. This new macro declare_cpu_ops_wa_4 allows support for new CVE check function. [1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I417389f040c6ead7f96f9b720d29061833f43d37
152 lines
4.8 KiB
C
152 lines
4.8 KiB
C
/*
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* Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CPU_OPS_H
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#define CPU_OPS_H
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#include <arch.h>
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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(MIDR_PN_MASK << MIDR_PN_SHIFT)
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/* Hardcode to keep compatible with assembly. sizeof(uintptr_t) */
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#if __aarch64__
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#define CPU_WORD_SIZE 8
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#else
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#define CPU_WORD_SIZE 4
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#endif /* __aarch64__ */
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/* The number of CPU operations allowed */
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#define CPU_MAX_PWR_DWN_OPS 2
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/* Special constant to specify that CPU has no reset function */
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#define CPU_NO_RESET_FUNC 0
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#if __aarch64__
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#define CPU_NO_EXTRA1_FUNC 0
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#define CPU_NO_EXTRA2_FUNC 0
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#define CPU_NO_EXTRA3_FUNC 0
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#define CPU_NO_EXTRA4_FUNC 0
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#endif /* __aarch64__ */
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/*
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* Define the sizes of the fields in the cpu_ops structure. Word size is set per
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* Aarch so keep these definitions the same and each can include whatever it
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* needs.
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*/
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#define CPU_MIDR_SIZE CPU_WORD_SIZE
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#ifdef IMAGE_AT_EL3
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#define CPU_RESET_FUNC_SIZE CPU_WORD_SIZE
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#else
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#define CPU_RESET_FUNC_SIZE 0
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#endif /* IMAGE_AT_EL3 */
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#define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE
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#define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE
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#define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE
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#define CPU_EXTRA4_FUNC_SIZE CPU_WORD_SIZE
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#define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE
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/* The power down core and cluster is needed only in BL31 and BL32 */
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#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
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#define CPU_PWR_DWN_OPS_SIZE CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
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#else
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#define CPU_PWR_DWN_OPS_SIZE 0
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#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
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#define CPU_ERRATA_LIST_START_SIZE CPU_WORD_SIZE
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#define CPU_ERRATA_LIST_END_SIZE CPU_WORD_SIZE
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/* Fields required to print errata status */
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#if REPORT_ERRATA
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#define CPU_CPU_STR_SIZE CPU_WORD_SIZE
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/* BL1 doesn't require mutual exclusion and printed flag. */
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#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
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#define CPU_ERRATA_LOCK_SIZE CPU_WORD_SIZE
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#define CPU_ERRATA_PRINTED_SIZE CPU_WORD_SIZE
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#else
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#define CPU_ERRATA_LOCK_SIZE 0
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#define CPU_ERRATA_PRINTED_SIZE 0
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#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
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#else
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#define CPU_CPU_STR_SIZE 0
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#define CPU_ERRATA_LOCK_SIZE 0
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#define CPU_ERRATA_PRINTED_SIZE 0
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#endif /* REPORT_ERRATA */
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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#define CPU_REG_DUMP_SIZE CPU_WORD_SIZE
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#else
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#define CPU_REG_DUMP_SIZE 0
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#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */
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/*
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* Define the offsets to the fields in cpu_ops structure. Every offset is
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* defined based on the offset and size of the previous field.
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*/
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#define CPU_MIDR 0
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#define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE
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#if __aarch64__
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#define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
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#define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
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#define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
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#define CPU_EXTRA4_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
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#define CPU_E_HANDLER_FUNC CPU_EXTRA4_FUNC + CPU_EXTRA4_FUNC_SIZE
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#define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
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#else
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#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
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#endif /* __aarch64__ */
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#define CPU_ERRATA_LIST_START CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
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#define CPU_ERRATA_LIST_END CPU_ERRATA_LIST_START + CPU_ERRATA_LIST_START_SIZE
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#define CPU_CPU_STR CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE
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#define CPU_ERRATA_LOCK CPU_CPU_STR + CPU_CPU_STR_SIZE
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#define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
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#if __aarch64__
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#define CPU_REG_DUMP CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
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#define CPU_OPS_SIZE CPU_REG_DUMP + CPU_REG_DUMP_SIZE
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#else
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#define CPU_OPS_SIZE CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
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#endif /* __aarch64__ */
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#ifndef __ASSEMBLER__
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#include <lib/cassert.h>
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#include <lib/spinlock.h>
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struct cpu_ops {
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unsigned long midr;
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#ifdef IMAGE_AT_EL3
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void (*reset_func)(void);
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#endif /* IMAGE_AT_EL3 */
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#if __aarch64__
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void (*extra1_func)(void);
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void (*extra2_func)(void);
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void (*extra3_func)(void);
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void (*extra4_func)(void);
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void (*e_handler_func)(long es);
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#endif /* __aarch64__ */
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#if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS
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void (*pwr_dwn_ops[CPU_MAX_PWR_DWN_OPS])(void);
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#endif /* (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS */
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void *errata_list_start;
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void *errata_list_end;
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#if REPORT_ERRATA
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char *cpu_str;
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#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
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spinlock_t *errata_lock;
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unsigned int *errata_reported;
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#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
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#endif /* REPORT_ERRATA */
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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void (*reg_dump)(void);
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#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */
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} __packed;
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CASSERT(sizeof(struct cpu_ops) == CPU_OPS_SIZE,
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assert_cpu_ops_asm_c_different_sizes);
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long cpu_get_rev_var(void);
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void *get_cpu_ops_ptr(void);
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#endif /* __ASSEMBLER__ */
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#endif /* CPU_OPS_H */
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