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https://github.com/ARM-software/arm-trusted-firmware.git
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f1fe1440db
Add platform specific interrupt handler for handling the reboot of all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into trusted firmware. The CPU which entered trusted firmware signals the rest of the cores which are online using SGI to initiate power down sequence. On receiving the SGI, the handler will power down the GIC redistributor interface of the respective core, configure the power control register and power down the CPU by executing wfi. In addition to these changes, fix coding style issues that are not directly related to the code being introduced in this patch. Change-Id: I4917dfdc47be5ce7367bee629486a6344cdd706f Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
64 lines
2.2 KiB
C
64 lines
2.2 KiB
C
/*
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* Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CSS_PM_H
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#define CSS_PM_H
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#include <cdefs.h>
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#include <stdint.h>
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#include <lib/psci/psci.h>
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/* SGI used to trigger per-core power down request */
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#define CSS_CPU_PWR_DOWN_REQ_INTR ARM_IRQ_SEC_SGI_7
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/* Macros to read the CSS power domain state */
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#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
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#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
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static inline unsigned int css_system_pwr_state(const psci_power_state_t *state)
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{
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#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL)
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return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL];
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#else
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return 0;
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#endif
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}
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int css_pwr_domain_on(u_register_t mpidr);
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void css_pwr_domain_on_finish(const psci_power_state_t *target_state);
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void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state);
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void css_pwr_domain_off(const psci_power_state_t *target_state);
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void css_pwr_domain_suspend(const psci_power_state_t *target_state);
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void css_pwr_domain_suspend_finish(
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const psci_power_state_t *target_state);
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void __dead2 css_system_off(void);
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void __dead2 css_system_reset(void);
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void css_cpu_standby(plat_local_state_t cpu_state);
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void css_get_sys_suspend_power_state(psci_power_state_t *req_state);
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int css_node_hw_state(u_register_t mpidr, unsigned int power_level);
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void css_setup_cpu_pwr_down_intr(void);
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int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags,
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void *handle, void *cookie);
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/*
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* This mapping array has to be exported by the platform. Each element at
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* a given index maps that core to an SCMI power domain.
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*/
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extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[];
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#define SCMI_DOMAIN_ID_MASK U(0xFFFF)
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#define SCMI_CHANNEL_ID_MASK U(0xFFFF)
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#define SCMI_CHANNEL_ID_SHIFT U(16)
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#define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \
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SCMI_CHANNEL_ID_SHIFT)
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#define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK)
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#define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \
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SCMI_CHANNEL_ID_MASK)
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#define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK)
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#endif /* CSS_PM_H */
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