Omkar Anand Kulkarni f1e4a28d3f feat(arm): enable FHI PPI interrupt to report CPU errors ... To handle the core corrected errors in the firmware, the FHI PPI interrupt has to be enabled on all the cores. At boot, when the RAS framework is initialized, only primary core is up and hence core FHI PPI interrupt is enabled only on primary core. This patch adds support to configure and enable core FHI interrupt for all the secondary cores as part of their boot sequence. Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656		2023-08-01 21:09:18 +05:30
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board	fvp_r: load, auth, and transfer from BL1 to BL33	2021-09-30 17:07:11 +01:00
common	feat(arm): enable FHI PPI interrupt to report CPU errors	2023-08-01 21:09:18 +05:30
css/common	feat(tc): allow secure watchdog timer to trigger periodically	2023-05-04 08:24:12 -05:00
soc/common	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00