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7f152ea685
Apply the mitigation only for the revision and variant mentioned in the SDEN. SDEN Documentation: https://developer.arm.com/documentation/SDEN859515/latest Change-Id: Ifda1f4cb32bdec9a9af29397ddc03bf22a7a87fc Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
175 lines
5.3 KiB
ArmAsm
175 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cortex_a75.h>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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.global check_erratum_cortex_a75_764081
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
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sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
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workaround_reset_end cortex_a75, ERRATUM(764081)
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check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0)
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workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748
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sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13)
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workaround_reset_end cortex_a75, ERRATUM(790748)
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check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0)
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/* ERRATA_DSU_798953 :
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* The errata is defined in dsu_helpers.S but applies to cortex_a75
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* as well. Henceforth creating symbolic names to the already existing errata
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* workaround functions to get them registered under the Errata Framework.
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*/
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.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953
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.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa
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add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
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/* ERRATA_DSU_936184 :
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* The errata is defined in dsu_helpers.S but applies to cortex_a75
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* as well. Henceforth creating symbolic names to the already existing errata
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* workaround functions to get them registered under the Errata Framework.
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*/
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.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184
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.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa
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add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
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workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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#if IMAGE_BL31
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override_vector_table wa_cve_2017_5715_bpiall_vbar
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a75, CVE(2017, 5715)
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check_erratum_custom_start cortex_a75, CVE(2017, 5715)
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cpu_check_csv2 x0, 1f
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#if WORKAROUND_CVE_2017_5715
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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check_erratum_custom_end cortex_a75, CVE(2017, 5715)
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workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
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workaround_reset_end cortex_a75, CVE(2018, 3639)
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check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/* Skip installing vector table again if already done for CVE(2017, 5715) */
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adr x0, wa_cve_2017_5715_bpiall_vbar
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mrs x1, vbar_el3
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cmp x0, x1
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b.eq 1f
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msr vbar_el3, x0
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1:
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a75, CVE(2022, 23960)
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check_erratum_custom_start cortex_a75, CVE(2022, 23960)
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#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
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cpu_check_csv2 x0, 1f
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mov x0, #ERRATA_APPLIES
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ret
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1:
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# if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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# else
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mov x0, #ERRATA_MISSING
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# endif /* WORKAROUND_CVE_2022_23960 */
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ret
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#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
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mov x0, #ERRATA_MISSING
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ret
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check_erratum_custom_end cortex_a75, CVE(2022, 23960)
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A75.
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* -------------------------------------------------
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*/
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cpu_reset_func_start cortex_a75
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT
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isb
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/* Enable group0 counters */
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mov x0, #CORTEX_A75_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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/* Enable group1 counters */
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mov x0, #CORTEX_A75_AMU_GROUP1_MASK
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msr CPUAMCNTENSET_EL0, x0
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/* isb included in cpu_reset_func_end macro */
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#endif
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cpu_reset_func_end cortex_a75
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func check_smccc_arch_workaround_3
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mov x0, #ERRATA_APPLIES
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ret
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endfunc check_smccc_arch_workaround_3
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a75_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \
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CORTEX_A75_CORE_PWRDN_EN_MASK
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isb
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ret
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endfunc cortex_a75_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a75 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a75_regs, "aS"
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cortex_a75_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a75_cpu_reg_dump
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adr x6, cortex_a75_regs
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mrs x8, CORTEX_A75_CPUECTLR_EL1
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ret
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endfunc cortex_a75_cpu_reg_dump
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declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
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cortex_a75_reset_func, \
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check_erratum_cortex_a75_5715, \
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CPU_NO_EXTRA2_FUNC, \
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check_smccc_arch_workaround_3, \
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cortex_a75_core_pwr_dwn
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