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8ae6b1ad6c
This patch implements SMCCC_ARCH_WORKAROUND_4 and allows discovery through SMCCC_ARCH_FEATURES. This mechanism is enabled if CVE_2024_7881 [1] is enabled by the platform. If CVE_2024_7881 mitigation is implemented, the discovery call returns 0, if not -1 (SMC_ARCH_CALL_NOT_SUPPORTED). For more information about SMCCC_ARCH_WORKAROUND_4 [2], please refer to the SMCCC Specification reference provided below. [1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881 [2]: https://developer.arm.com/documentation/den0028/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I1b1ffaa1f806f07472fd79d5525f81764d99bc79
171 lines
6.1 KiB
ArmAsm
171 lines
6.1 KiB
ArmAsm
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x3, CVE(2024, 5660)
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check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2)
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workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301
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sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \
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CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH
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workaround_reset_end cortex_x3, ERRATUM(2070301)
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check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
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workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
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sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
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workaround_reset_end cortex_x3, ERRATUM(2266875)
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check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0)
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workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506
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sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0)
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workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB
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check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1)
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workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
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sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
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workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
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check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
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workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204
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/* Set bit 40 in CPUACTLR2_EL1 */
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sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40)
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workaround_reset_end cortex_x3, ERRATUM(2372204)
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check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0)
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workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
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/* Disable retention control for WFI and WFE. */
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mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
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bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
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bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
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msr CORTEX_X3_CPUPWRCTLR_EL1, x0
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workaround_reset_end cortex_x3, ERRATUM(2615812)
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check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
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workaround_runtime_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945
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sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41)
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workaround_runtime_end cortex_x3, ERRATUM(2641945), NO_ISB
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check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0)
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workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
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sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56
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workaround_reset_end cortex_x3, ERRATUM(2742421)
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check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
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workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB
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check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1)
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workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509
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/* Set CPUACTLR3_EL1 bit 47 */
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sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47
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workaround_reset_end cortex_x3, ERRATUM(2779509)
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check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1)
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workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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override_vector_table wa_cve_vbar_cortex_x3
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_x3, CVE(2022, 23960)
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check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x3, CVE(2024, 7881)
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check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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cpu_reset_func_start cortex_x3
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_x3
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x3_core_pwr_dwn
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apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_x3_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-X3-
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* specific register information for crash
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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* and x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x3_regs, "aS"
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cortex_x3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x3_cpu_reg_dump
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adr x6, cortex_x3_regs
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mrs x8, CORTEX_X3_CPUECTLR_EL1
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ret
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endfunc cortex_x3_cpu_reg_dump
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declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \
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cortex_x3_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_cortex_x3_7881, \
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cortex_x3_core_pwr_dwn
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