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986c4e991a
To be able to further restrict the memory access for the Arm(R) Ethos(TM)-N NPU, separate read-only and read/write NSAIDs for the non-protected and protected memory have been added to the Juno platform's TZMP1 TZC configuration for the NPU. The platform definition has been updated accordingly and the NPU driver will now only give read/write access to the streams that require it. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I5a173500fc1943a5cd406a3b379e1f1f554eeda6
60 lines
2.4 KiB
C
60 lines
2.4 KiB
C
/*
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* Copyright (c) 2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef JUNO_ETHOSN_TZMP1_DEF_H
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#define JUNO_ETHOSN_TZMP1_DEF_H
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#define JUNO_ETHOSN_TZC400_NSAID_FW_PROT 7
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT 8
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT 13
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/* 0 is the default NSAID and is included in PLAT_ARM_TZC_NS_DEV_ACCESS */
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS 0
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS 14
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE UL(0x000400000) /* 4 MB */
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE (ARM_DRAM2_BASE)
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END (ARM_DRAM2_BASE + \
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JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE \
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- 1U)
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#define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE UL(0x004000000) /* 64 MB */
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#define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE ( \
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JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END + 1)
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#define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END ( \
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE + \
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE - 1U)
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#define JUNO_ETHOSN_NS_DRAM2_BASE (JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END + \
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1)
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#define JUNO_ETHOSN_NS_DRAM2_END (ARM_DRAM2_END)
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#define JUNO_ETHOSN_NS_DRAM2_SIZE (ARM_DRAM2_SIZE - \
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END)
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#define JUNO_FW_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_FW_PROT))
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#define JUNO_DATA_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT) | \
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TZC_REGION_ACCESS_RD(JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT))
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#define JUNO_DATA_TZC_NS_ACCESS \
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(PLAT_ARM_TZC_NS_DEV_ACCESS | \
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TZC_REGION_ACCESS_RD(JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS))
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#define JUNO_ETHOSN_TZMP_REGIONS_DEF \
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{ ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE, \
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TZC_REGION_S_RDWR, 0 }, \
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{ ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, JUNO_DATA_TZC_NS_ACCESS}, \
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{ JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \
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JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END, \
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TZC_REGION_S_RDWR, JUNO_FW_TZC_PROT_ACCESS }, \
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{ JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE, \
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END, \
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TZC_REGION_S_NONE, JUNO_DATA_TZC_PROT_ACCESS }, \
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{ JUNO_ETHOSN_NS_DRAM2_BASE, JUNO_ETHOSN_NS_DRAM2_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, JUNO_DATA_TZC_NS_ACCESS}
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#endif /* JUNO_ETHOSN_TZMP1_DEF_H */
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