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feat(ethos-n): add separate RO and RW NSAIDs
To be able to further restrict the memory access for the Arm(R) Ethos(TM)-N NPU, separate read-only and read/write NSAIDs for the non-protected and protected memory have been added to the Juno platform's TZMP1 TZC configuration for the NPU. The platform definition has been updated accordingly and the NPU driver will now only give read/write access to the streams that require it. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I5a173500fc1943a5cd406a3b379e1f1f554eeda6
This commit is contained in:
Mikael Olsson
Joanna Farley
parent
6dcf3e7744
commit
986c4e991a
4 changed files with 56 additions and 19 deletions
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@ -582,10 +582,25 @@ enabled, the following constants must also be defined.
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
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access the protected memory that contains the NPU's firmware.
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- **ARM_ETHOSN_NPU_PROT_DATA_NSAID**
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- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID**
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
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access the protected memory that contains inference data.
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
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read/write access to the protected memory that contains inference data.
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- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID**
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
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read-only access to the protected memory that contains inference data.
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- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID**
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
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read/write access to the non-protected memory.
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- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID**
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
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read-only access to the non-protected memory.
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- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT**
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@ -94,11 +94,12 @@
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#define SEC_NPU_ID_REG U(0xF000)
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#define SEC_NPU_ID_ARCH_VER_SHIFT U(0X10)
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#define FIRMWARE_STREAM_INDEX U(0x0)
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#define FIRMWARE_STREAM_INDEX U(0x0)
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#define WORKING_STREAM_INDEX U(0x1)
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#define PLE_STREAM_INDEX U(0x4)
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#define INPUT_STREAM_INDEX U(0x6)
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#define INTERMEDIATE_STREAM_INDEX U(0x7)
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#define OUTPUT_STREAM_INDEX U(0x8)
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#define INPUT_STREAM_INDEX U(0x6)
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#define INTERMEDIATE_STREAM_INDEX U(0x7)
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#define OUTPUT_STREAM_INDEX U(0x8)
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#define TO_EXTEND_ADDR(addr) \
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((addr >> SEC_ADDR_EXT_SHIFT) & SEC_ADDR_EXT_MASK)
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@ -154,16 +155,23 @@ static void ethosn_configure_stream_nsaid(const struct ethosn_core_t *core,
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bool is_protected)
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{
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size_t i;
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uint32_t streams[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
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uint32_t streams[9] = {[0 ... 8] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID};
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streams[FIRMWARE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
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streams[PLE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
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streams[WORKING_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
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if (is_protected) {
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streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_DATA_NSAID;
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streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID;
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streams[INTERMEDIATE_STREAM_INDEX] =
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ARM_ETHOSN_NPU_PROT_DATA_NSAID;
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streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_DATA_NSAID;
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ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
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streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
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} else {
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streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID;
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streams[INTERMEDIATE_STREAM_INDEX] =
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ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
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streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
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}
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for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
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@ -327,9 +327,14 @@
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/* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */
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#ifdef JUNO_ETHOSN_TZMP1
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#define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
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#define ARM_ETHOSN_NPU_PROT_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_PROT
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#define ARM_ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
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#define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
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#define ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
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#define ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
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#define ARM_ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
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#define ARM_ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
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#define ARM_ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
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#define ARM_ETHOSN_NPU_FW_IMAGE_LIMIT \
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(JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE)
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#endif
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@ -7,8 +7,13 @@
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#ifndef JUNO_ETHOSN_TZMP1_DEF_H
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#define JUNO_ETHOSN_TZMP1_DEF_H
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#define JUNO_ETHOSN_TZC400_NSAID_FW_PROT 7
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_PROT 8
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#define JUNO_ETHOSN_TZC400_NSAID_FW_PROT 7
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT 8
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT 13
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/* 0 is the default NSAID and is included in PLAT_ARM_TZC_NS_DEV_ACCESS */
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS 0
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS 14
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE UL(0x000400000) /* 4 MB */
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE (ARM_DRAM2_BASE)
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@ -32,13 +37,17 @@
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#define JUNO_FW_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_FW_PROT))
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#define JUNO_DATA_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_DATA_PROT))
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(TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT) | \
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TZC_REGION_ACCESS_RD(JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT))
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#define JUNO_DATA_TZC_NS_ACCESS \
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(PLAT_ARM_TZC_NS_DEV_ACCESS | \
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TZC_REGION_ACCESS_RD(JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS))
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#define JUNO_ETHOSN_TZMP_REGIONS_DEF \
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{ ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE, \
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TZC_REGION_S_RDWR, 0 }, \
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{ ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS }, \
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ARM_TZC_NS_DRAM_S_ACCESS, JUNO_DATA_TZC_NS_ACCESS}, \
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{ JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \
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JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END, \
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TZC_REGION_S_RDWR, JUNO_FW_TZC_PROT_ACCESS }, \
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@ -46,6 +55,6 @@
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END, \
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TZC_REGION_S_NONE, JUNO_DATA_TZC_PROT_ACCESS }, \
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{ JUNO_ETHOSN_NS_DRAM2_BASE, JUNO_ETHOSN_NS_DRAM2_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS }
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ARM_TZC_NS_DRAM_S_ACCESS, JUNO_DATA_TZC_NS_ACCESS}
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#endif /* JUNO_ETHOSN_TZMP1_DEF_H */
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