Arvind Ram Prakash 42d4d3baac refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 ... BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>		2023-03-15 11:43:14 +00:00
..
aarch64	feat(nxp/common): add CORTEX A53 helper functions	2022-01-19 11:36:23 +08:00
fip_handler	nxp: fip-handler for additional fip_fuse.bin	2021-03-24 09:49:32 +05:30
img_loadr	fix(layerscape): fix coverity issue	2022-03-30 10:38:22 +08:00
include/default	feat(layerscape): add soc helper macro definition for chassis 3	2022-03-27 23:24:24 +08:00
nv_storage	fix(layerscape): fix nv_storage assert checking	2022-11-22 16:35:19 +08:00
ocram	feat(nxp/common/ocram): add driver for OCRAM initialization	2021-10-09 10:57:54 +02:00
plat_make_helper	refactor(layerscape): refine comparison of inerconnection	2022-03-27 23:24:24 +08:00
psci	fix: unify fallthrough annotations	2022-12-01 16:17:24 +00:00
setup	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00
sip_svc	nxp: svp & sip smc handling	2021-03-24 09:49:32 +05:30
soc_errata	feat(layerscape): print DDR errata information	2022-03-27 23:24:24 +08:00
tbbr	fix: make TF-A use provided OpenSSL binary	2022-08-04 10:45:46 +01:00
warm_reset	nxp: warm reset support to retain ddr content	2021-03-24 09:49:32 +05:30