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42d4d3baac
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
175 lines
4.1 KiB
C
175 lines
4.1 KiB
C
/*
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* Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <drivers/arm/sbsa.h>
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#if SPM_MM
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#include <services/spm_mm_partition.h>
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#endif
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/*
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* Table of regions for different BL stages to map using the MMU.
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*/
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#if IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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SGI_MAP_FLASH0_RO,
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CSS_SGI_MAP_DEVICE,
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SOC_PLATFORM_PERIPH_MAP_DEVICE,
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SOC_SYSTEM_PERIPH_MAP_DEVICE,
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{0}
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};
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#endif
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#if IMAGE_BL2
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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SGI_MAP_FLASH0_RO,
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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CSS_SGI_MAP_DEVICE,
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SOC_MEMCNTRL_MAP_DEVICE,
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SOC_PLATFORM_PERIPH_MAP_DEVICE,
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SOC_SYSTEM_PERIPH_MAP_DEVICE,
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ARM_MAP_NS_DRAM1,
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#if CSS_SGI_CHIP_COUNT > 1
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SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1),
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#endif
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#if CSS_SGI_CHIP_COUNT > 2
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SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2),
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#endif
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#if CSS_SGI_CHIP_COUNT > 3
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SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3),
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#endif
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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#endif
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#if SPM_MM
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ARM_SP_IMAGE_MMAP,
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#endif
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#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
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ARM_MAP_BL1_RW,
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#endif
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{0}
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};
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#endif
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#if IMAGE_BL31
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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CSS_SGI_MAP_DEVICE,
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SOC_PLATFORM_PERIPH_MAP_DEVICE,
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SOC_SYSTEM_PERIPH_MAP_DEVICE,
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#if SPM_MM
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ARM_SPM_BUF_EL3_MMAP,
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#endif
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{0}
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};
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#if SPM_MM && defined(IMAGE_BL31)
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const mmap_region_t plat_arm_secure_partition_mmap[] = {
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PLAT_ARM_SECURE_MAP_SYSTEMREG,
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PLAT_ARM_SECURE_MAP_NOR2,
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SOC_PLATFORM_SECURE_UART,
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SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
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ARM_SP_IMAGE_MMAP,
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ARM_SP_IMAGE_NS_BUF_MMAP,
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ARM_SP_IMAGE_RW_MMAP,
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ARM_SPM_BUF_EL0_MMAP,
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{0}
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};
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#endif /* SPM_MM && defined(IMAGE_BL31) */
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#endif
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ARM_CASSERT_MMAP
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#if SPM_MM && defined(IMAGE_BL31)
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/*
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* Boot information passed to a secure partition during initialisation. Linear
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* indices in MP information will be filled at runtime.
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*/
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static spm_mm_mp_info_t sp_mp_info[] = {
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[0] = {0x81000000, 0},
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[1] = {0x81010000, 0},
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[2] = {0x81020000, 0},
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[3] = {0x81030000, 0},
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[4] = {0x81040000, 0},
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[5] = {0x81050000, 0},
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[6] = {0x81060000, 0},
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[7] = {0x81070000, 0},
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[8] = {0x81080000, 0},
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[9] = {0x81090000, 0},
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[10] = {0x810a0000, 0},
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[11] = {0x810b0000, 0},
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[12] = {0x810c0000, 0},
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[13] = {0x810d0000, 0},
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[14] = {0x810e0000, 0},
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[15] = {0x810f0000, 0},
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};
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const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
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.h.type = PARAM_SP_IMAGE_BOOT_INFO,
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.h.version = VERSION_1,
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.h.size = sizeof(spm_mm_boot_info_t),
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.h.attr = 0,
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.sp_mem_base = ARM_SP_IMAGE_BASE,
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.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
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.sp_image_base = ARM_SP_IMAGE_BASE,
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.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
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.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
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.sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
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.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
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.sp_image_size = ARM_SP_IMAGE_SIZE,
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.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
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.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
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.sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
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.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
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.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
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.num_cpus = PLATFORM_CORE_COUNT,
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.mp_info = &sp_mp_info[0],
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};
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const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
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{
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return plat_arm_secure_partition_mmap;
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}
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const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
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void *cookie)
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{
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return &plat_arm_secure_partition_boot_info;
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}
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#endif /* SPM_MM && defined(IMAGE_BL31) */
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#if TRUSTED_BOARD_BOOT
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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void plat_arm_secure_wdt_start(void)
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{
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sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
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}
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void plat_arm_secure_wdt_stop(void)
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{
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sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
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}
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